c05ba1e864
This usually shouldn't be used in Tiles that are meant to be P&R'd once and multiply instantiated, as their RTL would no longer be homogeneous. However, it is useful for conditionalizing RTL generation for heterogeneous tiles.
213 lines
6.4 KiB
Scala
213 lines
6.4 KiB
Scala
package groundtest
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import Chisel._
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import uncore.tilelink._
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import uncore.devices.NTiles
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import uncore.constants._
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import junctions._
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import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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case class GeneratorParameters(
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maxRequests: Int,
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startAddress: BigInt)
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case object GeneratorKey extends Field[GeneratorParameters]
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trait HasGeneratorParameters extends HasGroundTestParameters {
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implicit val p: Parameters
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val genParams = p(GeneratorKey)
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val nGens = p(GroundTestKey).map(
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cs => cs.uncached + cs.cached).reduce(_ + _)
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val genTimeout = 8192
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val maxRequests = genParams.maxRequests
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val startAddress = genParams.startAddress
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val genWordBits = 32
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val genWordBytes = genWordBits / 8
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val wordOffset = log2Ceil(genWordBytes)
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val wordSize = UInt(log2Ceil(genWordBytes))
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require(startAddress % BigInt(genWordBytes) == 0)
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}
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class UncachedTileLinkGenerator(id: Int)
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParameters {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val status = new GroundTestStatus
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}
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire(), maxRequests)
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val sending = Reg(init = Bool(false))
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when (state === s_start) {
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sending := Bool(true)
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state := s_put
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}
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (io.mem.grant.fire()) { sending := Bool(true) }
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when (req_wrap) { state := Mux(state === s_put, s_get, s_finished) }
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val timeout = Timer(genTimeout, io.mem.acquire.fire(), io.mem.grant.fire())
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assert(!timeout, s"Uncached generator ${id} timed out waiting for grant")
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io.status.finished := (state === s_finished)
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io.status.timeout.valid := timeout
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io.status.timeout.bits := UInt(id)
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val part_of_full_addr =
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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val full_addr = UInt(startAddress) + Cat(req_cnt, part_of_full_addr)
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val addr_block = full_addr >> UInt(tlBlockOffset)
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val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits)
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val addr_byte = full_addr(tlByteAddrBits - 1, 0)
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val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
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val word_data = Wire(UInt(width = genWordBits))
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word_data := Cat(data_prefix, part_of_full_addr)
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val beat_data = Fill(tlDataBits / genWordBits, word_data)
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val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset))
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val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift
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val put_acquire = Put(
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client_xact_id = UInt(0),
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = beat_data,
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wmask = Some(wmask),
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alloc = Bool(false))
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val get_acquire = Get(
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client_xact_id = UInt(0),
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addr_block = addr_block,
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addr_beat = addr_beat,
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addr_byte = addr_byte,
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operand_size = wordSize,
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alloc = Bool(false))
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io.mem.acquire.valid := sending && !io.status.finished
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.grant.ready := !sending && !io.status.finished
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def wordFromBeat(addr: UInt, dat: UInt) = {
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val shift = Cat(beatOffset(addr), UInt(0, wordOffset + 3))
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(dat >> shift)(genWordBits - 1, 0)
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}
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val data_mismatch = io.mem.grant.fire() && state === s_get &&
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wordFromBeat(full_addr, io.mem.grant.bits.data) =/= word_data
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io.status.error.valid := data_mismatch
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io.status.error.bits := UInt(id)
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assert(!data_mismatch,
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s"Get received incorrect data in uncached generator ${id}")
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def beatOffset(addr: UInt) = // TODO zero-width
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if (tlByteAddrBits > wordOffset) addr(tlByteAddrBits - 1, wordOffset)
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else UInt(0)
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}
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class HellaCacheGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParameters {
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val io = new Bundle {
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val mem = new HellaCacheIO
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val status = new GroundTestStatus
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}
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val timeout = Timer(genTimeout, io.mem.req.fire(), io.mem.resp.valid)
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assert(!timeout, s"Cached generator ${id} timed out waiting for response")
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io.status.timeout.valid := timeout
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io.status.timeout.bits := UInt(id)
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val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val sending = Reg(init = Bool(false))
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val (req_cnt, req_wrap) = Counter(io.mem.resp.valid, maxRequests)
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val part_of_req_addr =
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, part_of_req_addr)
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io.mem.req.valid := sending && !io.status.finished
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.data := req_data
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io.mem.req.bits.typ := wordSize
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io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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io.mem.req.bits.tag := UInt(0)
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when (state === s_start) { sending := Bool(true); state := s_write }
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when (io.mem.req.fire()) { sending := Bool(false) }
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when (io.mem.resp.valid) { sending := Bool(true) }
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when (req_wrap) { state := Mux(state === s_write, s_read, s_finished) }
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io.status.finished := (state === s_finished)
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def data_match(recv: Bits, expected: Bits): Bool = {
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val recv_resized = Wire(Bits(width = genWordBits))
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val exp_resized = Wire(Bits(width = genWordBits))
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recv_resized := recv
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exp_resized := expected
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recv_resized === exp_resized
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}
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val data_mismatch = io.mem.resp.valid && io.mem.resp.bits.has_data &&
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!data_match(io.mem.resp.bits.data, req_data)
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io.status.error.valid := data_mismatch
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io.status.error.bits := UInt(id)
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assert(!data_mismatch,
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s"Received incorrect data in cached generator ${id}")
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}
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class GeneratorTest(implicit p: Parameters)
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extends GroundTest()(p) with HasGeneratorParameters {
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val idStart = p(GroundTestKey).take(p(TileId))
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.map(settings => settings.cached + settings.uncached)
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.foldLeft(0)(_ + _)
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val cached = List.tabulate(nCached) { i =>
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val realId = idStart + i
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Module(new HellaCacheGenerator(realId))
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}
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val uncached = List.tabulate(nUncached) { i =>
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val realId = idStart + nCached + i
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Module(new UncachedTileLinkGenerator(realId))
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}
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io.cache <> cached.map(_.io.mem)
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io.mem <> uncached.map(_.io.mem)
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val gen_debug = cached.map(_.io.status) ++ uncached.map(_.io.status)
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io.status := DebugCombiner(gen_debug)
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}
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