dd4a50c452
Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
272 lines
8.1 KiB
Verilog
272 lines
8.1 KiB
Verilog
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module AsyncFifo (
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// Write Interface
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enq_clock
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, enq_reset
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, enq_ready
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, enq_valid
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, enq_bits
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// Read Interface
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, deq_clock
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, deq_reset
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, deq_ready
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, deq_valid
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, deq_bits
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);
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//--------------------------------------------------------
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// Parameter Declarations
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parameter DEPTH_LG_2 = 0; // default is 'mailbox'.
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parameter WIDTH = 64;
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localparam DEPTH = 2**DEPTH_LG_2;
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//--------------------------------------------------------
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// I/O Declarations
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// Write Interface
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input enq_clock;
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wire w_clock = enq_clock;
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input enq_reset;
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wire w_reset = enq_reset;
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output enq_ready;
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wire w_ready;
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assign enq_ready = w_ready;
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input enq_valid;
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wire w_valid = enq_valid;
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input [WIDTH - 1 : 0 ] enq_bits;
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wire [WIDTH - 1 : 0 ] w_bits = enq_bits;
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// Read Interface
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input deq_clock;
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wire r_clock = deq_clock;
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input deq_reset;
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wire r_reset = deq_reset;
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output deq_valid;
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wire r_valid;
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assign deq_valid = r_valid;
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input deq_ready;
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wire r_ready = deq_ready;
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output [WIDTH - 1 : 0] deq_bits;
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wire [WIDTH - 1 : 0] r_bits;
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assign deq_bits = r_bits;
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//--------------------------------------------------------
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// FIFO Memory Declaration
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generate
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if (DEPTH > 1) begin : mem1_scope
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reg [WIDTH - 1 : 0] fifoMem [ 0 : DEPTH - 1];
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end else begin : mem2_scope
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reg [WIDTH - 1 :0] fifoMem;
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end
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endgenerate
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//--------------------------------------------------------
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// Reg and Wire Declarations
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wire w_full;
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wire w_fire;
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wire r_empty;
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wire r_fire;
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// Read & Write Address Pointers
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generate
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if (DEPTH_LG_2 > 0) begin : reg1_scope
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reg [DEPTH_LG_2 : 0 ] w_wrAddrReg;
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wire [DEPTH_LG_2 : 0] w_wrAddrNxt;
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reg [DEPTH_LG_2 : 0 ] w_wrAddrGrayReg;
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wire [DEPTH_LG_2 : 0] w_wrAddrGrayNxt;
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reg [DEPTH_LG_2 : 0 ] r_rdAddrReg;
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wire [DEPTH_LG_2 : 0] r_rdAddrNxt;
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reg [DEPTH_LG_2 : 0 ] r_rdAddrGrayReg;
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wire [DEPTH_LG_2 : 0] r_rdAddrGrayNxt;
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reg [DEPTH_LG_2 : 0 ] wrAddrGrayReg_sync;
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reg [DEPTH_LG_2 : 0 ] rdAddrGrayReg_sync;
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reg [DEPTH_LG_2 : 0 ] r_wrAddrGrayReg;
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reg [DEPTH_LG_2 : 0 ] w_rdAddrGrayReg;
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end else begin : reg2_scope
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reg w_wrAddrReg;
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wire w_wrAddrNxt;
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reg r_rdAddrReg;
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wire r_rdAddrNxt;
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reg wrAddrReg_sync;
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reg rdAddrReg_sync;
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reg r_wrAddrReg;
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reg w_rdAddrReg;
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end
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endgenerate
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//--------------------------------------------------------
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// Reg and Wire Declarations
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// Pointer Logic
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generate
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if (DEPTH_LG_2 > 0) begin : ptr_logic_scope
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assign w_full = ~(reg1_scope.w_wrAddrGrayReg[DEPTH_LG_2] == reg1_scope.w_rdAddrGrayReg[DEPTH_LG_2]) &
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(reg1_scope.w_wrAddrGrayReg[DEPTH_LG_2 - 1 : 0] == reg1_scope.w_rdAddrGrayReg[DEPTH_LG_2 - 1 : 0 ]);
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assign reg1_scope.w_wrAddrNxt = reg1_scope.w_wrAddrReg + 1'b1; // OK / expected to overflow
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assign reg1_scope.w_wrAddrGrayNext = reg1_scope.w_wrAddrNxt ^ (reg1_scope.w_wrAddrNxt >> 1);
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assign reg1_scope.r_rdAddrNxt = reg1_scope.r_rdAddrReg + 1'b1; // OK / expected to overflow
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assign reg1_scope.r_rdAddrGrayNext = reg1_scope.r_rdAddrNxt ^ (reg1_scope.r_rdAddrNxt >> 1);
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assign r_empty = (reg1_scope.r_wrAddrGrayReg == reg1_scope.r_rdAddrGrayReg);
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end else begin : ptr_logic_scope
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assign w_full = ~(reg2_scope.w_wrAddrReg == reg2_scope.r_rdAddrReg);
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assign reg2_scope.w_wrAddrNxt = ~reg2_scope.w_wrAddrReg ;
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assign reg2_scope.r_rdAddrNxt = ~reg2_scope.r_rdAddrReg;
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assign r_empty = (reg2_scope.r_wrAddrReg == reg2_scope.r_rdAddrReg);
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end
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endgenerate
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assign w_ready = ~w_full;
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assign w_fire = w_ready & w_valid;
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// Read Logic
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assign r_valid = ~r_empty;
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assign r_fire = r_ready & r_valid;
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generate
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if (DEPTH > 1) begin : rw_scope1
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if (DEPTH > 2) begin : rw_scope2
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assign r_bits = mem1_scope.fifoMem[reg1_scope.r_rdAddrReg[DEPTH_LG_2-1:0]];
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always @(posedge w_clock) begin
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if (w_fire) begin
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mem1_scope.fifoMem[reg1_scope.w_wrAddrReg[DEPTH_LG_2-1:0]] <= w_bits;
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end
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end
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end else begin
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assign r_bits = mem1_scope.fifoMem[reg1_scope.r_rdAddrReg[0]];
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always @(posedge w_clock) begin
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if (w_fire) begin
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mem1_scope.fifoMem[reg1_scope.w_wrAddrReg[0]] <= w_bits;
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end
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end
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end
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end else begin
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assign r_bits = mem2_scope.fifoMem;
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always @(posedge w_clock) begin
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if (w_fire) begin
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mem2_scope.fifoMem <= w_bits;
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end
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end
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end
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endgenerate
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//--------------------------------------------------------
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// Sequential logic
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//
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generate
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if (DEPTH_LG_2 > 0) begin : seq1_scope
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always @(posedge w_clock or posedge w_reset) begin
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if (w_reset) begin
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reg1_scope.w_wrAddrReg <= 'b0;
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reg1_scope.w_wrAddrGrayReg <= 'b0;
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reg1_scope.rdAddrGrayReg_sync <= 'b0;
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reg1_scope.w_rdAddrGrayReg <= 'b0;
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end else begin
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if (w_fire) begin
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reg1_scope.w_wrAddrReg <= reg1_scope.w_wrAddrNxt;
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reg1_scope.w_wrAddrGrayReg <= reg1_scope.w_wrAddrGrayNxt;
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end
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reg1_scope.rdAddrGrayReg_sync <= reg1_scope.r_rdAddrGrayReg;
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reg1_scope.w_rdAddrGrayReg <= reg1_scope.rdAddrGrayReg_sync;
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end
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end
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always @(posedge r_clock or posedge r_reset) begin
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if (r_reset) begin
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reg1_scope.r_rdAddrReg <= 'b0;
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reg1_scope.r_rdAddrGrayReg <= 'b0;
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reg1_scope.reg1_scope.wrAddrGrayReg_sync <= 'b0;
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reg1_scope.reg1_scope.r_wrAddrGrayReg <= 'b0;
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end else begin
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if (r_fire) begin
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reg1_scope.r_rdAddrReg <= reg1_scope.r_rdAddrNxt;
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reg1_scope.r_rdAddrGrayReg <= reg1_scope.r_rdAddrGrayNxt;
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end
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reg1_scope.wrAddrGrayReg_sync <= reg1_scope.w_wrAddrGrayReg;
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reg1_scope.r_wrAddrGrayReg <= reg1_scope.wrAddrGrayReg_sync;
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end
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end // always @ (posedge r_clock)
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end else begin : seq2_scope // block: seq1_scope
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always @(posedge w_clock or posedge w_reset) begin
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if (w_reset ) begin
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reg2_scope.w_wrAddrReg <= 1'b0;
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reg2_scope.rdAddrReg_sync <= 1'b0;
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reg2_scope.w_rdAddrReg <= 1'b0;
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end else begin
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if (w_fire) begin
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reg2_scope.w_wrAddrReg <= reg2_scope.w_wrAddrNxt;
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end
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reg2_scope.rdAddrReg_sync <= reg2_scope.r_rdAddrReg;
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reg2_scope.w_rdAddrReg <= reg2_scope.rdAddrReg_sync;
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end
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end
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always @(posedge r_clock or posedge r_reset) begin
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if (r_reset) begin
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reg2_scope.r_rdAddrReg <= 1'b0;
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reg2_scope.wrAddrReg_sync <= 1'b0;
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reg2_scope.r_wrAddrReg <= 1'b0;
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end else begin
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if (r_fire) begin
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reg2_scope.r_rdAddrReg <= reg2_scope.r_rdAddrNxt;
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end
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reg2_scope.wrAddrReg_sync <= reg2_scope.w_wrAddrReg;
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reg2_scope.r_wrAddrReg <= reg2_scope.wrAddrReg_sync;
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end
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end // always @ (posedge r_clock)
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end // block: seq2_scope
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endgenerate
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endmodule // AsyncFifo
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