rocket-chip

History

Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86 ) It was possible that the result of a store-conditional could get lost if it did not depend on the result of the corresponding load-reserved. This was because the MSHR does not update the client state based on the secondary requests. So the LR would acquire the line in clientExcusiveClean, but then we would fail to update the metadata array to change the state to clientExclusiveDirty. The solution is to track whether a secondary acquire would cause the line to be dirty. If so, use M_XWR instead of the primary command to generate the update coherence state.	2016-07-26 18:41:52 -07:00
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main/scala	fix LRSC issue (RocketChip issue #86 )	2016-07-26 18:41:52 -07:00

Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86 )

It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.

2016-07-26 18:41:52 -07:00

main/scala

fix LRSC issue (RocketChip issue #86 )

2016-07-26 18:41:52 -07:00