55 lines
1.7 KiB
Scala
55 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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/** Implements the same interface as chisel3.util.Queue, but uses a shift
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* register internally. It is less energy efficient whenever the queue
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* has more than one entry populated, but is faster on the dequeue side.
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* It is efficient for usually-empty flow-through queues. */
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class ShiftQueue[T <: Data](gen: T,
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val entries: Int,
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pipe: Boolean = false,
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flow: Boolean = false)
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extends Module {
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val io = IO(new QueueIO(gen, entries) {
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val mask = UInt(OUTPUT, entries)
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})
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private val valid = RegInit(Vec.fill(entries) { Bool(false) })
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private val elts = Reg(Vec(entries, gen))
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for (i <- 0 until entries) {
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def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i)
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val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits)
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val wen =
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Mux(io.deq.ready,
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paddedValid(i+1) || io.enq.fire() && valid(i),
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io.enq.fire() && paddedValid(i-1) && !valid(i))
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when (wen) { elts(i) := wdata }
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valid(i) :=
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Mux(io.deq.ready,
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paddedValid(i+1) || io.enq.fire() && (Bool(i == 0 && !flow) || valid(i)),
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io.enq.fire() && paddedValid(i-1) || valid(i))
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}
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io.enq.ready := !valid(entries-1)
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io.deq.valid := valid(0)
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io.deq.bits := elts.head
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if (flow) {
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when (io.enq.valid) { io.deq.valid := true.B }
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when (!valid(0)) { io.deq.bits := io.enq.bits }
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}
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if (pipe) {
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when (io.deq.ready) { io.enq.ready := true.B }
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}
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io.mask := valid.asUInt
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io.count := PopCount(io.mask)
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}
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