Wesley W. Terpstra 710a782145 HeterogenousBag: empty bags were being combined! (#956) ...

This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.

2017-08-14 15:48:42 -07:00

..

Arbiters.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

AsyncBundle.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

AsyncQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

BlackBoxRegs.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Broadcaster.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ClockDivider.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Counters.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

CRC.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Crossing.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ECC.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Frequency.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

GeneratorUtils.scala

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

GenericParameterizedBundle.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

HellaQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

HeterogeneousBag.scala

HeterogenousBag: empty bags were being combined! (#956)

2017-08-14 15:48:42 -07:00

LatencyPipe.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

LCG.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Misc.scala

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

MultiWidthFifo.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

package.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

PlusArg.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

PositionalMultiQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

RationalCrossing.scala

util: tweak rational crossings to avoid mux in source

2017-07-31 15:10:15 -07:00

ReduceOthers.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ReorderQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Repeater.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Replacement.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ResetCatchAndSync.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

ROMGenerator.scala

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

ShiftQueue.scala

Optimize ShiftQueue for late-arriving deq.ready

2017-08-04 22:06:37 -07:00

Timer.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00