199 lines
11 KiB
Scala
199 lines
11 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait SubsystemClockCrossing
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{
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def sameClock = this match {
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case _: SynchronousCrossing => true
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case _ => false
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}
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}
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends SubsystemClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends SubsystemClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends SubsystemClockCrossing
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private case class CrossingCheck(out: Boolean, source: BaseNode, sink: BaseNode)
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trait HasCrossingMethods extends LazyModule with LazyScope
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{
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// Detect incorrect crossing connectivity
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private var checks: List[CrossingCheck] = Nil
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private def inside(node: BaseNode) = node.parents.exists(_ eq this)
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override def instantiate() {
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super.instantiate()
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checks.foreach { case CrossingCheck(out, source, sink) =>
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source.inputs.foreach { case (syncSource, _) =>
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require (inside(syncSource) == out, s"${syncSource.name} must ${if(out)""else"not "}be inside ${name} (wrong .cross direction?)")
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}
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sink.outputs.foreach { case (syncSink, _) =>
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require (inside(syncSink) != out, s"${syncSink.name} must ${if(out)"not "else""}be inside ${name} (wrong .cross direction?)")
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}
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}
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}
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// TileLink
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def crossTLSyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = {
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val sync_xing = this { LazyModule(new TLBuffer(params)).node }
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checks = CrossingCheck(out, sync_xing, sync_xing) :: checks
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sync_xing
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}
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def crossTLAsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = {
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lazy val async_xing_source = LazyModule(new TLAsyncCrossingSource(sync))
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lazy val async_xing_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { async_xing_source } else async_xing_source
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val sink = if (out) async_xing_sink else this { async_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossTLRationalInOut(out: Boolean)(direction: RationalDirection)(implicit p: Parameters): TLNode = {
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lazy val rational_xing_source = LazyModule(new TLRationalCrossingSource)
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lazy val rational_xing_sink = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
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val source = if (out) this { rational_xing_source } else rational_xing_source
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val sink = if (out) rational_xing_sink else this { rational_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossTLSyncIn (params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = crossTLSyncInOut(false)(params)
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def crossTLSyncOut(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = crossTLSyncInOut(true )(params)
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def crossTLAsyncIn (depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = crossTLAsyncInOut(false)(depth, sync)
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def crossTLAsyncOut(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = crossTLAsyncInOut(true )(depth, sync)
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def crossTLRationalIn (direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(false)(direction)
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def crossTLRationalOut(direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(true )(direction)
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def crossTLIn(arg: SubsystemClockCrossing)(implicit p: Parameters): TLNode = arg match {
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case x: SynchronousCrossing => crossTLSyncIn(x.params)
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case x: AsynchronousCrossing => crossTLAsyncIn(x.depth, x.sync)
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case x: RationalCrossing => crossTLRationalIn(x.direction)
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}
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def crossTLOut(arg: SubsystemClockCrossing)(implicit p: Parameters): TLNode = arg match {
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case x: SynchronousCrossing => crossTLSyncOut(x.params)
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case x: AsynchronousCrossing => crossTLAsyncOut(x.depth, x.sync)
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case x: RationalCrossing => crossTLRationalOut(x.direction)
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}
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// AXI4
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def crossAXI4SyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = {
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val axi4_sync_xing = this { LazyModule(new AXI4Buffer(params)).node }
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checks = CrossingCheck(out, axi4_sync_xing, axi4_sync_xing) :: checks
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axi4_sync_xing
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}
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def crossAXI4AsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = {
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lazy val axi4_async_xing_source = LazyModule(new AXI4AsyncCrossingSource(sync))
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lazy val axi4_async_xing_sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
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val source = if (out) this { axi4_async_xing_source } else axi4_async_xing_source
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val sink = if (out) axi4_async_xing_sink else this { axi4_async_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossAXI4SyncIn (params: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = crossAXI4SyncInOut(false)(params)
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def crossAXI4SyncOut(params: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = crossAXI4SyncInOut(true )(params)
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def crossAXI4AsyncIn (depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = crossAXI4AsyncInOut(false)(depth, sync)
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def crossAXI4AsyncOut(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = crossAXI4AsyncInOut(true )(depth, sync)
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def crossAXI4In(arg: SubsystemClockCrossing)(implicit p: Parameters): AXI4Node = arg match {
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case x: SynchronousCrossing => crossAXI4SyncIn(x.params)
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case x: AsynchronousCrossing => crossAXI4AsyncIn(x.depth, x.sync)
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case x: RationalCrossing => throw new IllegalArgumentException("AXI4 Rational crossing unimplemented")
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}
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def crossAXI4Out(arg: SubsystemClockCrossing)(implicit p: Parameters): AXI4Node = arg match {
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case x: SynchronousCrossing => crossAXI4SyncOut(x.params)
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case x: AsynchronousCrossing => crossAXI4AsyncOut(x.depth, x.sync)
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case x: RationalCrossing => throw new IllegalArgumentException("AXI4 Rational crossing unimplemented")
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}
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// Interrupts
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def crossIntSyncInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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lazy val int_sync_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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lazy val int_sync_xing_sink = LazyModule(new IntSyncCrossingSink(0))
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val source = if (out) this { int_sync_xing_source } else int_sync_xing_source
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val sink = if (out) int_sync_xing_sink else this { int_sync_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossIntAsyncInOut(out: Boolean)(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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lazy val int_async_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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lazy val int_async_xing_sink = LazyModule(new IntSyncCrossingSink(sync))
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val source = if (out) this { int_async_xing_source } else int_async_xing_source
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val sink = if (out) int_async_xing_sink else this { int_async_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossIntRationalInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
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lazy val int_rational_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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lazy val int_rational_xing_sink = LazyModule(new IntSyncCrossingSink(1))
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val source = if (out) this { int_rational_xing_source } else int_rational_xing_source
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val sink = if (out) int_rational_xing_sink else this { int_rational_xing_sink }
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sink.node :*=* source.node
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checks = CrossingCheck(out, source.node, sink.node) :: checks
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NodeHandle(source.node, sink.node)
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}
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def crossIntSyncIn (alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntSyncInOut(false)(alreadyRegistered)
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def crossIntSyncOut(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntSyncInOut(true )(alreadyRegistered)
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def crossIntAsyncIn (sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntAsyncInOut(false)(sync, alreadyRegistered)
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def crossIntAsyncOut(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntAsyncInOut(true )(sync, alreadyRegistered)
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def crossIntRationalIn (alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(false)(alreadyRegistered)
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def crossIntRationalOut(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(true )(alreadyRegistered)
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def crossIntIn(arg: SubsystemClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match {
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case x: SynchronousCrossing => crossIntSyncIn(alreadyRegistered)
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case x: AsynchronousCrossing => crossIntAsyncIn(x.sync, alreadyRegistered)
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case x: RationalCrossing => crossIntRationalIn(alreadyRegistered)
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}
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def crossIntOut(arg: SubsystemClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match {
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case x: SynchronousCrossing => crossIntSyncOut(alreadyRegistered)
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case x: AsynchronousCrossing => crossIntAsyncOut(x.sync, alreadyRegistered)
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case x: RationalCrossing => crossIntRationalOut(alreadyRegistered)
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}
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def crossIntIn (arg: SubsystemClockCrossing)(implicit p: Parameters): IntNode = crossIntIn (arg, false)
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def crossIntOut(arg: SubsystemClockCrossing)(implicit p: Parameters): IntNode = crossIntOut(arg, false)
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}
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trait HasCrossing extends HasCrossingMethods
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{
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this: LazyModule =>
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val crossing: SubsystemClockCrossing
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def crossTLIn (implicit p: Parameters): TLNode = crossTLIn (crossing)
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def crossTLOut (implicit p: Parameters): TLNode = crossTLOut (crossing)
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def crossAXI4In (implicit p: Parameters): AXI4Node= crossAXI4In (crossing)
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def crossAXI4Out(implicit p: Parameters): AXI4Node= crossAXI4Out(crossing)
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def crossIntIn (implicit p: Parameters): IntNode = crossIntIn (crossing)
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def crossIntOut (implicit p: Parameters): IntNode = crossIntOut (crossing)
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def crossIntIn (alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = crossIntIn (crossing, alreadyRegistered)
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def crossIntOut(alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = crossIntOut(crossing, alreadyRegistered)
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}
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class CrossingWrapper(val crossing: SubsystemClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossing
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