82 lines
1.6 KiB
Verilog
82 lines
1.6 KiB
Verilog
// See LICENSE.SiFive for license details.
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/** This black-boxes an Async Reset
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* Reg.
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*
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* Because Chisel doesn't support
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* parameterized black boxes,
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* we unfortunately have to
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* instantiate a number of these.
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*
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* We also have to hard-code the set/reset.
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*
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* Do not confuse an asynchronous
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* reset signal with an asynchronously
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* reset reg. You should still
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* properly synchronize your reset
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* deassertion.
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*
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* @param d Data input
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* @param q Data Output
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* @param clk Clock Input
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* @param rst Reset Input
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* @param en Write Enable Input
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*
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*/
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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module AsyncResetReg (
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input d,
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output reg q,
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input en,
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input clk,
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input rst);
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initial begin
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`ifdef RANDOMIZE
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integer initvar;
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reg [31:0] _RAND;
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_RAND = {1{$random}};
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`endif
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if (rst) begin
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`ifdef verilator
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q = 1'b0;
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`endif
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end
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`ifdef RANDOMIZE
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`ifndef verilator
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`endif
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`ifdef RANDOMIZE_REG_INIT
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else begin
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#0.002 begin end
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q = _RAND[0];
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end
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`endif
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`endif // `ifdef RANDOMIZE
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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q <= 1'b0;
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end else if (en) begin
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q <= d;
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end
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end
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endmodule // AsyncResetReg
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