rocket-chip/src/main/scala at cedfb0e784d4a6fac5346a77e7fc1ad069948b7d - rocket-chip - Tiband Gitea

riscv/rocket-chip

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T

History

Henry Cook cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire

which contains hartid.

2017-10-02 19:36:10 -07:00

..

diplomacy: standardize sram device resource naming (#1022 )

2017-09-29 14:52:26 -07:00

config: fix warning

2017-09-22 14:58:36 -07:00

coreplex: dontTouch the rocket_tile_inputs wire

2017-10-02 19:36:10 -07:00

clint: output interrupts in the correct direction

2017-09-27 15:18:42 -07:00

diplomacy: standardize sram device resource naming (#1022 )

2017-09-29 14:52:26 -07:00

rocket: invoke LazyModule at point of use/binding

2017-09-22 14:38:47 -07:00

Bump chisel3 and firrtl, update plugin versions

2017-09-29 15:44:27 -07:00

add cloneType to RegisterWriteIO and RegisterReadIO (#874 )

2017-07-18 18:52:31 -07:00

Merge pull request #1020 from freechipsproject/fix-trace-insn

2017-09-27 18:47:24 -07:00

config: use Field defaults over Config defaults

2017-09-13 11:25:42 -07:00

rocket: move interrupt synchronizers to correct side of crossing

2017-09-27 12:02:04 -07:00

diplomacy: standardize sram device resource naming (#1022 )

2017-09-29 14:52:26 -07:00

diplomacy: change API to auto-create node bundles => cross-module refs

2017-09-22 15:01:39 -07:00

util: add Option.unzip

2017-09-25 12:06:31 -07:00