Howard Mao cd96a66ba6 replace verilog clock divider with one written in Chisel		2016-09-22 11:32:29 -07:00
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coreplex	simplify base Coreplex bundle	2016-09-21 18:29:28 -07:00
groundtest	rename internal/external MMIO network to cbus/pbus respectively	2016-09-21 18:29:28 -07:00
junctions	add multiclock support to Coreplex	2016-09-21 16:55:26 -07:00
rocket	rename internal/external MMIO network to cbus/pbus respectively	2016-09-21 18:29:28 -07:00
rocketchip	simplify base Coreplex bundle	2016-09-21 18:29:28 -07:00
uncore	replace verilog clock divider with one written in Chisel	2016-09-22 11:32:29 -07:00
unittest	make sure junctions and uncore unittests both run	2016-09-21 20:17:52 -07:00
util	replace verilog clock divider with one written in Chisel	2016-09-22 11:32:29 -07:00