e8c8d2af71
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
169 lines
6.6 KiB
Scala
169 lines
6.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import tile._
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import util._
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class ExpandedInstruction extends Bundle {
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val bits = UInt(width = 32)
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val rd = UInt(width = 5)
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val rs1 = UInt(width = 5)
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val rs2 = UInt(width = 5)
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val rs3 = UInt(width = 5)
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}
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class RVCDecoder(x: UInt)(implicit p: Parameters) {
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def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
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val res = Wire(new ExpandedInstruction)
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res.bits := bits
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res.rd := rd
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res.rs1 := rs1
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res.rs2 := rs2
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res.rs3 := rs3
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res
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}
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def rs1p = Cat(UInt(1,2), x(9,7))
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def rs2p = Cat(UInt(1,2), x(4,2))
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def rs2 = x(6,2)
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def rd = x(11,7)
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def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), UInt(0,2))
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def lwImm = Cat(x(5), x(12,10), x(6), UInt(0,2))
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def ldImm = Cat(x(6,5), x(12,10), UInt(0,3))
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def lwspImm = Cat(x(3,2), x(12), x(6,4), UInt(0,2))
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def ldspImm = Cat(x(4,2), x(12), x(6,5), UInt(0,3))
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def swspImm = Cat(x(8,7), x(12,9), UInt(0,2))
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def sdspImm = Cat(x(9,7), x(12,10), UInt(0,3))
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def luiImm = Cat(Fill(15, x(12)), x(6,2), UInt(0,12))
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def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), UInt(0,4))
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def addiImm = Cat(Fill(7, x(12)), x(6,2))
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def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), UInt(0,1))
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def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), UInt(0,1))
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def shamt = Cat(x(12), x(6,2))
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def x0 = UInt(0,5)
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def ra = UInt(1,5)
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def sp = UInt(2,5)
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def q0 = {
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def addi4spn = {
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val opc = Mux(x(12,5).orR, UInt(0x13,7), UInt(0x1F,7))
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inst(Cat(addi4spnImm, sp, UInt(0,3), rs2p, opc), rs2p, sp, rs2p)
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}
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def ld = inst(Cat(ldImm, rs1p, UInt(3,3), rs2p, UInt(0x03,7)), rs2p, rs1p, rs2p)
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def lw = inst(Cat(lwImm, rs1p, UInt(2,3), rs2p, UInt(0x03,7)), rs2p, rs1p, rs2p)
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def fld = inst(Cat(ldImm, rs1p, UInt(3,3), rs2p, UInt(0x07,7)), rs2p, rs1p, rs2p)
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def flw = {
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if (p(XLen) == 32) inst(Cat(lwImm, rs1p, UInt(2,3), rs2p, UInt(0x07,7)), rs2p, rs1p, rs2p)
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else ld
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}
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def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, UInt(2,3), lwImm(4,0), UInt(0x2F,7)), rs2p, rs1p, rs2p)
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def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, UInt(3,3), ldImm(4,0), UInt(0x23,7)), rs2p, rs1p, rs2p)
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def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, UInt(2,3), lwImm(4,0), UInt(0x23,7)), rs2p, rs1p, rs2p)
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def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, UInt(3,3), ldImm(4,0), UInt(0x27,7)), rs2p, rs1p, rs2p)
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def fsw = {
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if (p(XLen) == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, UInt(2,3), lwImm(4,0), UInt(0x27,7)), rs2p, rs1p, rs2p)
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else sd
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}
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Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
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}
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def q1 = {
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def addi = inst(Cat(addiImm, rd, UInt(0,3), rd, UInt(0x13,7)), rd, rd, rs2p)
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def addiw = {
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val opc = Mux(rd.orR, UInt(0x1B,7), UInt(0x1F,7))
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inst(Cat(addiImm, rd, UInt(0,3), rd, opc), rd, rd, rs2p)
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}
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def jal = {
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if (p(XLen) == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, UInt(0x6F,7)), ra, rd, rs2p)
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else addiw
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}
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def li = inst(Cat(addiImm, x0, UInt(0,3), rd, UInt(0x13,7)), rd, x0, rs2p)
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def addi16sp = {
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val opc = Mux(addiImm.orR, UInt(0x13,7), UInt(0x1F,7))
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inst(Cat(addi16spImm, rd, UInt(0,3), rd, opc), rd, rd, rs2p)
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}
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def lui = {
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val opc = Mux(addiImm.orR, UInt(0x37,7), UInt(0x3F,7))
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val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
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Mux(rd === x0 || rd === sp, addi16sp, me)
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}
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def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, UInt(0x6F,7)), x0, rs1p, rs2p)
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def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, UInt(0,3), bImm(4,1), bImm(11), UInt(0x63,7)), rs1p, rs1p, x0)
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def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, UInt(1,3), bImm(4,1), bImm(11), UInt(0x63,7)), x0, rs1p, x0)
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def arith = {
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def srli = Cat(shamt, rs1p, UInt(5,3), rs1p, UInt(0x13,7))
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def srai = srli | UInt(1 << 30)
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def andi = Cat(addiImm, rs1p, UInt(7,3), rs1p, UInt(0x13,7))
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def rtype = {
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val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
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val sub = Mux(x(6,5) === UInt(0), UInt(1 << 30), UInt(0))
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val opc = Mux(x(12), UInt(0x3B,7), UInt(0x33,7))
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Cat(rs2p, rs1p, funct, rs1p, opc) | sub
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}
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inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
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}
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Seq(addi, jal, li, lui, arith, j, beqz, bnez)
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}
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def q2 = {
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def slli = inst(Cat(shamt, rd, UInt(1,3), rd, UInt(0x13,7)), rd, rd, rs2)
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def ldsp = inst(Cat(ldspImm, sp, UInt(3,3), rd, UInt(0x03,7)), rd, sp, rs2)
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def lwsp = inst(Cat(lwspImm, sp, UInt(2,3), rd, UInt(0x03,7)), rd, sp, rs2)
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def fldsp = inst(Cat(ldspImm, sp, UInt(3,3), rd, UInt(0x07,7)), rd, sp, rs2)
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def flwsp = {
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if (p(XLen) == 32) inst(Cat(lwspImm, sp, UInt(2,3), rd, UInt(0x07,7)), rd, sp, rs2)
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else ldsp
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}
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def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, UInt(3,3), sdspImm(4,0), UInt(0x23,7)), rd, sp, rs2)
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def swsp = inst(Cat(swspImm >> 5, rs2, sp, UInt(2,3), swspImm(4,0), UInt(0x23,7)), rd, sp, rs2)
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def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, UInt(3,3), sdspImm(4,0), UInt(0x27,7)), rd, sp, rs2)
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def fswsp = {
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if (p(XLen) == 32) inst(Cat(swspImm >> 5, rs2, sp, UInt(2,3), swspImm(4,0), UInt(0x27,7)), rd, sp, rs2)
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else sdsp
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}
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def jalr = {
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val mv = inst(Cat(rs2, x0, UInt(0,3), rd, UInt(0x33,7)), rd, x0, rs2)
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val add = inst(Cat(rs2, rd, UInt(0,3), rd, UInt(0x33,7)), rd, rd, rs2)
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val jr = Cat(rs2, rd, UInt(0,3), x0, UInt(0x67,7))
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val reserved = Cat(jr >> 7, UInt(0x1F,7))
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val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
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val jr_mv = Mux(rs2.orR, mv, jr_reserved)
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val jalr = Cat(rs2, rd, UInt(0,3), ra, UInt(0x67,7))
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val ebreak = Cat(jr >> 7, UInt(0x73,7)) | UInt(1 << 20)
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val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
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val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
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Mux(x(12), jalr_add, jr_mv)
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}
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Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
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}
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def q3 = Seq.fill(8)(passthrough)
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def passthrough = inst(x)
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def decode = {
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val s = q0 ++ q1 ++ q2 ++ q3
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s(Cat(x(1,0), x(15,13)))
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}
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}
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class RVCExpander(implicit val p: Parameters) extends Module with HasCoreParameters {
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val io = new Bundle {
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val in = UInt(INPUT, 32)
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val out = new ExpandedInstruction
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val rvc = Bool(OUTPUT)
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}
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if (usingCompressed) {
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io.rvc := io.in(1,0) =/= UInt(3)
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io.out := new RVCDecoder(io.in).decode
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} else {
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io.rvc := Bool(false)
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io.out := new RVCDecoder(io.in).passthrough
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}
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}
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