Wesley W. Terpstra cbf0670156 tilelink2 Legacy: it's only an error if it's valid

2016-09-08 19:32:00 -07:00

..

Buffer.scala

tilelink2: helper objects should pass source line from where they were invoked

2016-09-05 20:58:41 -07:00

Bundles.scala

tilelink2 Bundles: fix wrong sink width!

2016-09-08 13:47:40 -07:00

Edges.scala

TL2 WidthWidget (#258)

2016-09-08 10:38:38 -07:00

Fragmenter.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

GPIO.scala

tilelink2: move files to new uncore directory

2016-09-05 20:58:40 -07:00

HintHandler.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

LazyModule.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

Legacy.scala

tilelink2 Legacy: it's only an error if it's valid

2016-09-08 19:32:00 -07:00

Monitor.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

Nodes.scala

tilelink2: move files to new uncore directory

2016-09-05 20:58:40 -07:00

package.scala

TL2 WidthWidget (#258)

2016-09-08 10:38:38 -07:00

Parameters.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

RegField.scala

tilelink2 RegField: add a w1ToClear RegField

2016-09-08 14:02:49 -07:00

RegisterRouter.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

RegMapper.scala

tilelink2: ensure RegFields don't exceed their bounds

2016-09-05 20:58:40 -07:00

SRAM.scala

TL2 WidthWidget (#258)

2016-09-08 10:38:38 -07:00

TLNodes.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

WidthWidget.scala

TL2 WidthWidget (#258)

2016-09-08 10:38:38 -07:00

Xbar.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00