riscv/rocket-chip
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rocket-chip/src/main/scala/tile
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Wesley W. Terpstra eadf4e9fcc Revert "tile: add option for tile boundary buffers" 
This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
2017-07-29 00:03:24 -07:00
..
BaseTile.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Core.scala Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
FPU.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Interrupts.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
L1Cache.scala Combine Coreplex and System Module Hierarchies (#875) 2017-07-23 08:31:04 -07:00
LazyRoCC.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
RocketTile.scala Revert "tile: add option for tile boundary buffers" 2017-07-29 00:03:24 -07:00