116 lines
3.1 KiB
Scala
116 lines
3.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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/** These wrap behavioral
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* shift registers into specific
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* modules to allow for
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* backend flows to replace or constrain
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* them properly when used for CDC synchronization,
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* rather than buffering.
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*
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* The 3 different types vary in their reset behavior:
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* AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
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* SynchronizerShiftRegInit -- synchronously reset to 0
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* SynchronizerShiftReg -- no reset, pipeline only.
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*
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*/
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abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module {
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require(sync > 0, "Sync must be greater than 0.")
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val io = new Bundle {
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val d = UInt(INPUT, width = w)
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val q = UInt(OUTPUT, width = w)
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}
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}
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object AbstractSynchronizerReg {
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def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
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val sync_reg = Module(gen(in.getWidth, sync))
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name.foreach{ sync_reg.suggestName(_) }
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sync_reg.io.d := in.asUInt
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(in.chiselCloneType).fromBits(sync_reg.io.q)
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}
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}
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class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
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override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
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val syncv = List.tabulate(sync) { i =>
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Module (new AsyncResetRegVec(w, 0)).suggestName(s"sync_${i}")
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}
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syncv.last.io.d := io.d
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syncv.last.io.en := Bool(true)
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(syncv.init zip syncv.tail).foreach { case (sink, source) =>
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sink.io.d := source.io.q
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sink.io.en := Bool(true)
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}
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io.q := syncv.head.io.q
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}
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object AsyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new AsyncResetSynchronizerShiftReg(w, sync)},
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in, sync, name)
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}
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class SynchronizerShiftRegInit(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
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override def desiredName = s"SynchronizerShiftRegInit_w${w}_d${sync}"
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val syncv = List.tabulate(sync) { i =>
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val r = RegInit(UInt(0, width = w))
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r.suggestName(s"sync_${i}")
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}
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syncv.last := io.d
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(syncv.init zip syncv.tail).foreach { case (sink, source) =>
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sink := source
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}
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io.q := syncv.head
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}
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object SynchronizerShiftRegInit {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftRegInit(w, sync)},
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in, sync, name)
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}
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class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
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override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
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val syncv = List.tabulate(sync) { i =>
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val r = Reg(UInt(width = w))
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r.suggestName(s"sync_${i}")
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}
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syncv.last := io.d
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(syncv.init zip syncv.tail).foreach { case (sink, source) =>
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sink := source
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}
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io.q := syncv.head
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}
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object SynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftReg(w, sync)},
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in, sync, name)
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}
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