Megan Wachs c78ee9f0e4 syncreg: Refactor common code

2017-08-24 17:18:04 -07:00

..

amba

tilelink: Error device supports Acquire

2017-07-27 18:32:58 -07:00

config

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

coreplex

tilelink: make bus xbar protected so it can be suggestNamed

2017-08-07 17:30:24 -07:00

devices

jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed

2017-08-14 17:25:47 -07:00

diplomacy

diplomacy: seal the LazyModuleImpLike trait (#927)

2017-08-06 17:32:23 -07:00

groundtest

chiplink: adjust bus view to include the splitter (#886)

2017-07-24 21:41:17 -07:00

jtag

Use chisel3 Clock() method.

2017-07-07 14:16:39 -07:00

regmapper

add cloneType to RegisterWriteIO and RegisterReadIO (#874)

2017-07-18 18:52:31 -07:00

rocket

Remove redundant check in interrupt priority encoding

2017-08-17 22:23:42 -07:00

system

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

tile

Fixing requirements for PAddrBits (#961)

2017-08-17 11:53:59 -07:00

tilelink

PatternPusher: can now expect a certain output (#952)

2017-08-11 18:10:27 -07:00

unittest

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

util

syncreg: Refactor common code

2017-08-24 17:18:04 -07:00