Wesley W. Terpstra c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering

2016-10-13 17:02:17 -07:00

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coreplex

Disable U-mode by default unless S-mode is present

2016-10-08 21:29:40 -07:00

diplomacy

diplomacy: simplify address range fragmentation

2016-10-11 22:36:21 -07:00

groundtest

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

junctions

change the configuration interface of SlowIO

2016-09-29 22:16:53 -07:00

regmapper

regmapper: detect improper reset sequencing in RegisterCrossing

2016-10-10 13:13:32 -07:00

rocket

Fix an overly strict D$ assertion

2016-10-06 15:52:46 -07:00

rocketchip

debug: use a different form of the crossing which doesn't create an AsyncScope (#394)

2016-10-09 20:33:18 -07:00

uncore

tilelink2 Monitor: enforce stricter transaction ordering

2016-10-13 17:02:17 -07:00

unittest

axi4: include unit tests

2016-10-12 17:08:52 -07:00

util

AsyncQueue: adjust register names to match vals

2016-10-10 13:13:32 -07:00