102 lines
3.9 KiB
Scala
102 lines
3.9 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import uncore.devices._
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import util.ParameterizedBundle
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import rocket._
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import rocket.Util._
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import coreplex._
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// the following parameters will be refactored properly with TL2
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case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
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case object ConfigString extends Field[GlobalVariable[String]]
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case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
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/** Base Top with no Periphery */
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abstract class BaseTop(val p: Parameters) extends LazyModule {
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// the following variables will be refactored properly with TL2
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val pInterrupts = new RangeManager
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val pBusMasters = new RangeManager
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val pDevices = new ResourceManager[AddrMapEntry]
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}
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class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
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val success = c.hasSuccessFlag.option(Bool(OUTPUT))
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}
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
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val outer: L = l
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val c = CoreplexConfig(
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nTiles = p(NTiles),
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nExtInterrupts = outer.pInterrupts.sum,
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nSlaves = outer.pBusMasters.sum,
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nMemChannels = p(NMemoryChannels),
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hasSupervisor = p(UseVM),
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hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
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)
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def genGlobalAddrMap = GenerateGlobalAddrMap(p, outer.pDevices.get)
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def genConfigString = GenerateConfigString(p, c, outer.pDevices.get)
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p(NCoreplexExtClients).assign(outer.pBusMasters.sum)
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p(GlobalAddrMap).assign(genGlobalAddrMap)
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p(ConfigString).assign(genConfigString)
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).get.flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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println(f"\t$name%s $start%x - $end%x")
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}
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println("Generated Configuration String")
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println(p(ConfigString).get)
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val coreplex = p(BuildCoreplex)(p, c)
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val io: B = b(coreplex)
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io.success zip coreplex.io.success map { case (x, y) => x := y }
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val mmioNetwork = c.hasExtMMIOPort.option(
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Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
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p.alterPartial({ case TLId => "L2toMMIO" }))))
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mmioNetwork.foreach { _.io.in.head <> coreplex.io.master.mmio.get }
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}
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/** Example Top with Periphery */
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class ExampleTop(p: Parameters) extends BaseTop(p)
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with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
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with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
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override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
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}
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class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
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with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
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with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
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with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
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with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM(p: Parameters) extends ExampleTop(p)
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with PeripheryTestRAM {
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override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
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}
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class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
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with PeripheryTestRAMBundle
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class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
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with PeripheryTestRAMModule
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