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riscv/rocket-chip
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c366007a0d04193ae60988efb5d730e01333eef8
rocket-chip/src/main/scala
T
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Andrew WatermanandAndrew Waterman c366007a0d Tighten PMAs for LR/SC and misaligned accesses
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
debug: Make it easier to override parts of the Default Debug Config (#655)
2017-04-06 10:33:17 -07:00
diplomacy
diplomacy: use circles for nodes again
2017-04-14 18:09:14 -07:00
groundtest
Fix regression in groundtest DummyPTW
2017-03-28 00:56:14 -07:00
jtag
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
rocket
Tighten PMAs for LR/SC and misaligned accesses
2017-04-18 00:47:58 -07:00
rocketchip
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
tile
Fix whitespace error
2017-04-14 01:03:11 -07:00
uncore
debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores.
2017-04-17 10:28:33 -07:00
unittest
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
util
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
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