Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. ... This is simpler than JTAGVPI and is supported better by Verilor. It is also the same thing Spike uses.		2018-01-05 16:02:52 -08:00
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Configs.scala	Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.	2018-01-05 16:02:52 -08:00
ExampleRocketSystem.scala	rocket: don't remove ports on top module	2017-10-10 21:28:59 -07:00
Generator.scala	generator: create annotation file	2017-10-10 23:23:06 -07:00
RocketTestSuite.scala	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
TestHarness.scala	rocket: don't remove ports on top module	2017-10-10 21:28:59 -07:00