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rocket-chip/src/main/scala/devices/tilelink
Wesley W. Terpstra fa412246b3 Error: don't be an exception wrt. caching
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
..
BootROM.scala diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
BusBlocker.scala BusBlocker: don't provide an (incorrect) default value for width 2017-11-18 14:33:00 -08:00
BusBypass.scala Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
Clint.scala RegFieldDesc: Clean up both descriptions and JSON presentations 2018-02-11 23:57:57 -08:00
Error.scala Error: don't be an exception wrt. caching 2018-02-14 23:02:55 -08:00
MaskROM.scala diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Plic.scala PLIC: correct some descriptions 2018-02-12 08:31:29 -08:00
TestRAM.scala diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Zero.scala diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00