40 lines
1.3 KiB
Scala
40 lines
1.3 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.Config
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.rocket.{DCacheParams}
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import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
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/** Actual testing target Configs */
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class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseCoreplexConfig)
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class TraceGenBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new TraceGenConfig)
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/* Composable Configs to set individual parameters */
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class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config((site, here, up) => {
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case GroundTestTilesKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 32,
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addrBag = {
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val nSets = 2
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val nWays = 1
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = site(SystemBusKey).blockBeats
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).base,
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numGens = params.size)
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}
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case MaxHartIdBits => log2Up(params.size)
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})
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