131 lines
4.6 KiB
Scala
131 lines
4.6 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
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class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
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{
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// HintAcks can come back combinationally => minLatency=0
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => if (!supportClients) c else c.copy(minLatency = 0, clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
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managerFn = { case Seq(m) => if (!supportManagers) m else m.copy(minLatency = 0, managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val in = io.in(0)
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val out = io.out(0)
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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// Don't add support for clients if there is no BCE channel
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val bce = edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe
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require (!supportClients || bce)
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// Does it even make sense to add the HintHandler?
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val smartClients = edgeIn.client.clients.map(_.supportsHint.max == edgeIn.client.maxTransfer).reduce(_&&_)
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val smartManagers = edgeOut.manager.managers.map(_.supportsHint.max == edgeOut.manager.maxTransfer).reduce(_&&_)
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if (supportManagers && !(passthrough && smartManagers)) {
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHintFast(address, edgeIn.size(in.a.bits)) else Bool(true)
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val hintBitsAtA = handleA && in.a.bits.opcode === TLMessages.Hint
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val hint = Wire(out.d)
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hint.valid := in.a.valid && hintBitsAtA
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out.a.valid := in.a.valid && !hintBitsAtA
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in.a.ready := Mux(hintBitsAtA, hint.ready, out.a.ready)
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hint.bits := edgeIn.HintAck(in.a.bits, edgeOut.manager.findIdStartFast(address))
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out.a.bits := in.a.bits
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TLArbiter(TLArbiter.lowestIndexFirst)(in.d, (edgeOut.numBeats1(out.d.bits), out.d), (UInt(0), hint))
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} else {
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready
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out.a.bits := in.a.bits
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in.d.valid := out.d.valid
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out.d.ready := in.d.ready
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in.d.bits := out.d.bits
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}
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if (supportClients && !(passthrough && smartClients)) {
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val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source, edgeOut.size(out.b.bits)) else Bool(true)
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val hintBitsAtB = handleB && out.b.bits.opcode === TLMessages.Hint
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val hint = Wire(in.c)
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hint.valid := out.b.valid && hintBitsAtB
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in.b.valid := out.b.valid && !hintBitsAtB
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out.b.ready := Mux(hintBitsAtB, hint.ready, in.b.ready)
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hint.bits := edgeOut.HintAck(out.b.bits)
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in.b.bits := out.b.bits
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TLArbiter(TLArbiter.lowestIndexFirst)(out.c, (edgeIn.numBeats1(in.c.bits), in.c), (UInt(0), hint))
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} else if (bce) {
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in.b.valid := out.b.valid
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out.b.ready := in.b.ready
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in.b.bits := out.b.bits
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out.c.valid := in.c.valid
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in.c.ready := out.c.ready
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out.c.bits := in.c.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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}
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if (bce) {
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// Pass E through unchanged
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out.e.valid := in.e.valid
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in.e.ready := out.e.ready
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out.e.bits := in.e.bits
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} else {
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in.e.ready := Bool(true)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLHintHandler
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{
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// applied to the TL source node; y.node := TLHintHandler(x.node)
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def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
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val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
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hints.node := x
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hints.node
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}
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}
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/** Synthesizeable unit tests */
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import unittest._
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//TODO ensure handler will pass through hints to clients that can handle them themselves
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class TLRAMHintHandler() extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel)
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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ram.node := TLFragmenter(4, 256)(TLHintHandler()(model.node))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMHintHandlerTest extends UnitTest(timeout = 500000) {
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io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
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}
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