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rocket-chip/src/main/scala
Wesley W. Terpstra 38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager
This lets smart caches exclude the sets that are filtered.
2017-01-21 13:23:07 -08:00
..
config Configs: use a uniform syntax without Match exceptions (#507) 2017-01-13 14:41:19 -08:00
coreplex BankedL2: move TLFilter BEFORE coherence manager 2017-01-21 13:23:07 -08:00
diplomacy diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
groundtest coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
junctions Refactor Tile to use cake pattern (#502) 2017-01-16 18:24:08 -08:00
regmapper copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
rocket rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
rocketchip coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
uncore diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
unittest Refactor Tile to use cake pattern (#502) 2017-01-16 18:24:08 -08:00
util diplomacy: make config.Parameters available in bundle connect() 2016-12-07 12:24:01 -08:00