70 lines
1.8 KiB
Scala
70 lines
1.8 KiB
Scala
package referencechip
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import Chisel._
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import ReferenceChipBackend._
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import scala.collection.mutable.HashMap
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object ReferenceChipBackend {
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val initMap = new HashMap[Module, Bool]()
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}
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class ReferenceChipBackend extends VerilogBackend
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{
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initMap.clear()
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override def emitPortDef(m: MemAccess, idx: Int) = {
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val res = new StringBuilder()
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for (node <- m.mem.inputs) {
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if(node.name.contains("init"))
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res.append(" .init(" + node.name + "),\n")
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}
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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def addMemPin(c: Module) = {
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for (mod <- Module.components; node <- mod.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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connectMemPin(c, node.component, node)
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}
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}
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}
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def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
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var isNewPin = false
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val compInitPin =
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if (initMap.contains(c)) {
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initMap(c)
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} else {
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isNewPin = true
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val res = Bool(INPUT)
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res.isIo = true
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res
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}
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p.inputs += compInitPin
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if (isNewPin) {
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compInitPin.setName("init")
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c.io.asInstanceOf[Bundle] += compInitPin
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compInitPin.component = c
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initMap += (c -> compInitPin)
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connectMemPin(topC, c.parent, compInitPin)
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}
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}
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def addTopLevelPin(c: Module) = {
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val init = Bool(INPUT)
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init.isIo = true
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init.setName("init")
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init.component = c
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c.io.asInstanceOf[Bundle] += init
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initMap += (c -> init)
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}
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transforms += ((c: Module) => addTopLevelPin(c))
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transforms += ((c: Module) => addMemPin(c))
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transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
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}
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class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform
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