76 lines
1.9 KiB
C++
76 lines
1.9 KiB
C++
// See LICENSE for license details.
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#ifndef _MM_EMULATOR_DRAMSIM2_H
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#define _MM_EMULATOR_DRAMSIM2_H
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#include "mm.h"
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#include <DRAMSim.h>
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#include <map>
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#include <queue>
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#include <stdint.h>
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class mm_dramsim2_t : public mm_t
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{
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public:
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mm_dramsim2_t() : store_inflight(false) {}
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virtual void init(size_t sz, int word_size, int line_size);
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virtual bool ar_ready() { return mem->willAcceptTransaction(); }
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virtual bool aw_ready() { return mem->willAcceptTransaction() && !store_inflight; }
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virtual bool w_ready() { return store_inflight; }
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virtual bool b_valid() { return !bresp.empty(); }
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virtual uint64_t b_resp() { return 0; }
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virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; }
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virtual bool r_valid() { return !rresp.empty(); }
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virtual uint64_t r_resp() { return 0; }
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virtual uint64_t r_id() { return r_valid() ? rresp.front().id: 0; }
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virtual void *r_data() { return r_valid() ? &rresp.front().data[0] : &dummy_data[0]; }
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virtual bool r_last() { return r_valid() ? rresp.front().last : false; }
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virtual void tick
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(
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bool ar_valid,
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uint64_t ar_addr,
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uint64_t ar_id,
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uint64_t ar_size,
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uint64_t ar_len,
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bool aw_valid,
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uint64_t aw_addr,
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uint64_t aw_id,
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uint64_t aw_size,
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uint64_t aw_len,
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bool w_valid,
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uint64_t w_strb,
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void *w_data,
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bool w_last,
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bool r_ready,
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bool b_ready
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);
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protected:
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DRAMSim::MultiChannelMemorySystem *mem;
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uint64_t cycle;
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bool store_inflight;
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uint64_t store_addr;
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uint64_t store_id;
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uint64_t store_size;
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uint64_t store_count;
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std::vector<char> dummy_data;
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std::queue<uint64_t> bresp;
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std::map<uint64_t, std::queue<uint64_t> > wreq;
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std::map<uint64_t, std::queue<mm_rresp_t> > rreq;
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std::queue<mm_rresp_t> rresp;
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void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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void write_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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};
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#endif
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