201e247f73
This would allow, for instance, putting the coreplex on a separate clock domain and crossing the IOs over through asynchronous queues. The ExampleMultiClockTop* classes are removed since they no longer fit into the class hierarchy.
54 lines
1.8 KiB
Scala
54 lines
1.8 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import coreplex._
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import rocketchip._
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/** Example Top with Periphery */
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class ExampleTop(q: Parameters) extends BaseTop(q)
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with PeripheryBootROM
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with PeripheryDebug
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with PeripheryExtInterrupts
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with PeripheryCoreplexLocalInterrupter
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with PeripheryMasterMem
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with PeripheryMasterMMIO
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with PeripherySlave {
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override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p)))
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}
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class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
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with PeripheryBootROMBundle
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with PeripheryDebugBundle
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with PeripheryExtInterruptsBundle
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with PeripheryCoreplexLocalInterrupterBundle
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with PeripheryMasterMemBundle
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with PeripheryMasterMMIOBundle
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with PeripherySlaveBundle
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B) extends BaseTopModule(p, l, b)
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with PeripheryBootROMModule
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with PeripheryDebugModule
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with PeripheryExtInterruptsModule
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with PeripheryCoreplexLocalInterrupterModule
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with PeripheryMasterMemModule
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with PeripheryMasterMMIOModule
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with PeripherySlaveModule
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with HardwiredResetVector
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with DirectConnection
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
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with PeripheryTestRAM {
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override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p)))
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}
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class ExampleTopWithTestRAMBundle(p: Parameters) extends ExampleTopBundle(p)
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with PeripheryTestRAMBundle
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class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b)
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with PeripheryTestRAMModule
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