Wesley W. Terpstra 7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first		2016-10-17 01:00:49 -07:00
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coreplex	Disable U-mode by default unless S-mode is present	2016-10-08 21:29:40 -07:00
diplomacy	diplomacy: simplify address range fragmentation	2016-10-11 22:36:21 -07:00
groundtest	tilelink2: move general-purpose code out of tilelink2 package	2016-10-03 16:22:28 -07:00
junctions	change the configuration interface of SlowIO	2016-09-29 22:16:53 -07:00
regmapper	regmapper RegisterCrossing: safe AsyncQueues are overkill here	2016-10-14 18:28:31 -07:00
rocket	Fix an overly strict D$ assertion	2016-10-06 15:52:46 -07:00
rocketchip	debug: use a different form of the crossing which doesn't create an AsyncScope (#394)	2016-10-09 20:33:18 -07:00
uncore	axi4 ToTL: shorter critical path on Q.bits if errors go first	2016-10-17 01:00:49 -07:00
unittest	axi4: Test ToTL	2016-10-16 22:04:06 -07:00
util	AsyncQueue: cope with far reset propagation delay	2016-10-14 18:05:35 -07:00