rocket-chip/src/main/scala at 9e0c26f85544cf1a8c5fedd5656857b891855fd6 - rocket-chip - Tiband Gitea

riscv/rocket-chip

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Henry Cook f3575404c0 tile: bus blocker needs to know width :(

2017-11-17 20:17:17 -08:00

..

AXI4Xbar: reduce number of special cases

2017-11-14 15:09:09 -08:00

config: fix warning

2017-09-22 14:58:36 -07:00

tile: put a BasicBusBlocker inside RocketTile (#1115 )

2017-11-17 17:26:48 -08:00

tile: put a BasicBusBlocker inside RocketTile (#1115 )

2017-11-17 17:26:48 -08:00

diplomacy: define only primary node types

2017-10-28 11:16:56 -07:00

tile: put a BasicBusBlocker inside RocketTile (#1115 )

2017-11-17 17:26:48 -08:00

interrupts: Crossing should use asynchronously reset registers (#1080 )

2017-10-31 16:29:06 -07:00

JTAG: Use sorted map for stability (#1073 )

2017-10-31 15:33:41 -07:00

RegField: default argument for .bytes

2017-10-10 19:49:35 -07:00

tile: bus blocker needs to know width :(

2017-11-17 20:17:17 -08:00

coreplex: WithStatelessBridge => WithIncoherentTiles (#1092 )

2017-11-07 13:47:56 -08:00

tile: put a BasicBusBlocker inside RocketTile (#1115 )

2017-11-17 17:26:48 -08:00

tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111 )

2017-11-14 17:49:10 -08:00

unittest: include AXI4Xbar in regression

2017-11-14 15:09:09 -08:00

Merge pull request #1098 from freechipsproject/frontend

2017-11-09 17:44:38 -08:00