123 lines
3.9 KiB
Scala
123 lines
3.9 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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case object LNEndpoints extends Field[Int]
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case object LNHeaderBits extends Field[Int]
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class PhysicalHeader(n: Int) extends Bundle {
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val src = UInt(width = log2Up(n))
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val dst = UInt(width = log2Up(n))
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}
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class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
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val header = new PhysicalHeader(n)
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val payload = dType.cloneType
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override def cloneType = new PhysicalNetworkIO(n,dType).asInstanceOf[this.type]
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}
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class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
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val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip
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val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType)))
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}
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abstract class PhysicalNetwork extends Module
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case class CrossbarConfig[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None)
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abstract class AbstractCrossbar[T <: Data](conf: CrossbarConfig[T]) extends PhysicalNetwork {
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val io = new BasicCrossbarIO(conf.n, conf.dType)
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}
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class BasicBus[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
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val arb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
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arb.io.in <> io.in
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arb.io.out.ready := io.out(arb.io.out.bits.header.dst).ready
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for ((out, i) <- io.out zipWithIndex) {
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out.valid := arb.io.out.valid && arb.io.out.bits.header.dst === UInt(i)
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out.bits := arb.io.out.bits
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}
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}
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class BasicCrossbar[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
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io.in.foreach { _.ready := Bool(false) }
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io.out.zipWithIndex.map{ case (out, i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
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(rrarb.io.in, io.in).zipped.map{ case (arb, in) => {
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val destined = in.bits.header.dst === UInt(i)
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arb.valid := in.valid && destined
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arb.bits := in.bits
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when (arb.ready && destined) { in.ready := Bool(true) }
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}}
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out <> rrarb.io.out
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}}
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}
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abstract class LogicalNetwork extends Module
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class LogicalHeader(implicit p: Parameters) extends junctions.ParameterizedBundle()(p) {
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val src = UInt(width = p(LNHeaderBits))
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val dst = UInt(width = p(LNHeaderBits))
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}
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class LogicalNetworkIO[T <: Data](dType: T)(implicit p: Parameters) extends Bundle {
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val header = new LogicalHeader
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val payload = dType.cloneType
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override def cloneType = new LogicalNetworkIO(dType)(p).asInstanceOf[this.type]
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}
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object DecoupledLogicalNetworkIOWrapper {
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def apply[T <: Data](
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in: DecoupledIO[T],
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src: UInt = UInt(0),
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dst: UInt = UInt(0))
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(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Wire(Decoupled(new LogicalNetworkIO(in.bits)))
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out.valid := in.valid
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out.bits.payload := in.bits
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out.bits.header.dst := dst
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out.bits.header.src := src
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in.ready := out.ready
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out
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}
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}
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object DecoupledLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])
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(implicit p: Parameters): DecoupledIO[T] = {
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val out = Wire(Decoupled(in.bits.payload))
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out.valid := in.valid
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out.bits := in.bits.payload
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in.ready := out.ready
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out
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}
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}
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object DefaultFromPhysicalShim {
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def apply[T <: Data](in: DecoupledIO[PhysicalNetworkIO[T]])
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(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Wire(Decoupled(new LogicalNetworkIO(in.bits.payload)))
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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object DefaultToPhysicalShim {
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def apply[T <: Data](n: Int, in: DecoupledIO[LogicalNetworkIO[T]])
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(implicit p: Parameters): DecoupledIO[PhysicalNetworkIO[T]] = {
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val out = Wire(Decoupled(new PhysicalNetworkIO(n, in.bits.payload)))
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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