Scott Johnson f382ee70da Sanity check compile-time vs simulation-time options ... If user compiles without +define+DEBUG but then requests +vcdfile at simulation time, that request would be silently ignored. This changes it to a fatal error. It's good philosophy to treat plusargs like +vcdfile as commands, not suggestions, and die immediately if they cannot be honored, instead of silently ignoring them. Otherwise the user sits through the entire simulation and then is left scratching his head wondering where his waveforms are.		2016-10-24 14:45:34 -07:00
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AsyncResetReg.v	util: Do BlackBox Async Set/Reset Registers more properly (#305)	2016-09-16 13:50:09 -07:00
DebugTransportModuleJtag.v	jtag: Actually apply the sticky bits	2016-09-29 13:49:34 -07:00
jtag_vpi.tab	Add JTAG DTM and test support in simulation	2016-08-19 16:08:17 -07:00
jtag_vpi.v	fix warnings in verilog source (#274)	2016-09-12 18:25:35 -07:00
SimDTM.v	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
TestDriver.v	Sanity check compile-time vs simulation-time options	2016-10-24 14:45:34 -07:00