279 lines
9.7 KiB
Scala
279 lines
9.7 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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case class ICacheConfig(sets: Int, assoc: Int,
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ntlb: Int = 8, nbtb: Int = 8,
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code: Code = new IdentityCode)
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{
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val w = 1
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val ibytes = 4
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val dm = assoc == 1
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val lines = sets * assoc
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val databits = MEM_DATA_BITS
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val idxbits = log2Up(sets)
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val offbits = OFFSET_BITS
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val untagbits = idxbits + offbits
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val tagbits = PADDR_BITS - untagbits
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require(isPow2(sets) && isPow2(assoc))
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require(isPow2(w) && isPow2(ibytes))
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require(PGIDX_BITS >= untagbits)
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}
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class FrontendReq extends Bundle {
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val pc = UInt(width = VADDR_BITS+1)
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val mispredict = Bool()
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val taken = Bool()
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val currentpc = UInt(width = VADDR_BITS+1)
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}
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class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
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val pc = UInt(width = VADDR_BITS+1) // ID stage PC
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val data = Bits(width = conf.ibytes*8)
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val taken = Bool()
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val xcpt_ma = Bool()
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val xcpt_if = Bool()
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override def clone = new FrontendResp().asInstanceOf[this.type]
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}
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class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val ptw = new TLBPTWIO().flip
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val invalidate = Bool(OUTPUT)
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}
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class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
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{
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val io = new Bundle {
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val cpu = new CPUFrontendIO()(c).flip
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val mem = new UncachedTileLinkIO
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}
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val btb = Module(new rocketDpathBTB(c.nbtb))
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val icache = Module(new ICache)
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val tlb = Module(new TLB(c.ntlb))
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val s1_pc_ = Reg(UInt())
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val s1_pc = s1_pc_ & SInt(-2) // discard LSB of PC (throughout the pipeline)
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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val s2_btb_hit = Reg(init=Bool(false))
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val s2_xcpt_if = Reg(init=Bool(false))
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val btbTarget = Cat(btb.io.target(VADDR_BITS-1), btb.io.target)
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val pcp4_0 = s1_pc + UInt(c.ibytes)
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val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0))
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val icmiss = s2_valid && !icache.io.resp.valid
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val predicted_npc = Mux(btb.io.hit, btbTarget, pcp4)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && (predicted_npc >> log2Up(c.databits/8)) === (s1_pc >> log2Up(c.databits/8))
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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s1_same_block := s0_same_block && !tlb.io.resp.miss
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s1_pc_ := npc
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s2_valid := !icmiss
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when (!icmiss) {
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s2_pc := s1_pc
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s2_btb_hit := btb.io.hit
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s2_xcpt_if := tlb.io.resp.xcpt_if
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}
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}
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when (io.cpu.req.valid) {
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s1_same_block := Bool(false)
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s1_pc_ := io.cpu.req.bits.pc
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s2_valid := Bool(false)
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}
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btb.io.current_pc := s1_pc
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btb.io.wen := io.cpu.req.bits.mispredict
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btb.io.clr := !io.cpu.req.bits.taken
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btb.io.correct_pc := io.cpu.req.bits.currentpc
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btb.io.correct_target := io.cpu.req.bits.pc
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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tlb.io.ptw <> io.cpu.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> UInt(PGIDX_BITS)
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tlb.io.req.bits.asid := UInt(0)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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icache.io.mem <> io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8))
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io.cpu.resp.bits.taken := s2_btb_hit
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UInt(0)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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}
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class ICacheReq extends Bundle {
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val idx = UInt(width = PGIDX_BITS)
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val ppn = UInt(width = PPN_BITS) // delayed one cycle
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val kill = Bool() // delayed one cycle
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}
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class ICacheResp(implicit c: ICacheConfig) extends Bundle {
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val data = Bits(width = c.ibytes*8)
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val datablock = Bits(width = c.databits)
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override def clone = new ICacheResp().asInstanceOf[this.type]
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}
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class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
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{
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implicit val lnConf = tl.ln
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val io = new Bundle {
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val req = Valid(new ICacheReq).flip
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val resp = Decoupled(new ICacheResp)
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val invalidate = Bool(INPUT)
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val mem = new UncachedTileLinkIO
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}
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val stall = !io.resp.ready
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val rdy = Bool()
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val s2_valid = Reg(init=Bool(false))
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val s2_addr = Reg(UInt(width = PADDR_BITS))
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val s2_any_tag_hit = Bool()
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val s1_valid = Reg(init=Bool(false))
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val s1_pgoff = Reg(UInt(width = PGIDX_BITS))
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val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt
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val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
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val s0_valid = io.req.valid || s1_valid && stall
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val s0_pgoff = Mux(io.req.valid, io.req.bits.idx, s1_pgoff)
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s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
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when (io.req.valid && rdy) {
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s1_pgoff := s0_pgoff
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}
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s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall
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when (s1_valid && rdy && !stall) {
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s2_addr := s1_addr
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}
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val s2_tag = s2_addr(c.tagbits+c.untagbits-1,c.untagbits)
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val s2_idx = s2_addr(c.untagbits-1,c.offbits)
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val s2_offset = s2_addr(c.offbits-1,0)
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val s2_hit = s2_valid && s2_any_tag_hit
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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//assert(!co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
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val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES)
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val repl_way = if (c.dm) UInt(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
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val enc_tagbits = c.code.width(c.tagbits)
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val tag_array = Mem(Bits(width = enc_tagbits*c.assoc), c.sets, seqRead = true)
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val tag_raddr = Reg(UInt())
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when (refill_done) {
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val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UIntToOH(repl_way))
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val tag = c.code.encode(s2_tag).toUInt
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tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
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}
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// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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.elsewhen (s0_valid) {
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tag_raddr := s0_pgoff(c.untagbits-1,c.offbits)
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}
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val vb_array = Reg(init=Bits(0, c.lines))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
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}
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when (io.invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s2_disparity = Vec.fill(c.assoc){Bool()}
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for (i <- 0 until c.assoc)
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when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
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val s1_tag_match = Vec.fill(c.assoc){Bool()}
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val s2_tag_hit = Vec.fill(c.assoc){Bool()}
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val s2_dout = Vec.fill(c.assoc){Reg(Bits())}
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for (i <- 0 until c.assoc) {
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val s1_vb = vb_array(Cat(UInt(i), s1_pgoff(c.untagbits-1,c.offbits))).toBool
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val s2_vb = Reg(Bool())
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val s2_tag_disparity = Reg(Bool())
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val s2_tag_match = Reg(Bool())
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val tag_out = tag_array(tag_raddr)(enc_tagbits*(i+1)-1, enc_tagbits*i)
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when (s1_valid && rdy && !stall) {
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s2_vb := s1_vb
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s2_tag_disparity := c.code.decode(tag_out).error
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s2_tag_match := s1_tag_match(i)
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}
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s1_tag_match(i) := tag_out(c.tagbits-1,0) === s1_tag
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s2_tag_hit(i) := s2_vb && s2_tag_match
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s2_disparity(i) := s2_vb && (s2_tag_disparity || c.code.decode(s2_dout(i)).error)
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}
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s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
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for (i <- 0 until c.assoc) {
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val data_array = Mem(Bits(width = c.code.width(c.databits)), c.sets*REFILL_CYCLES, seqRead = true)
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val s1_raddr = Reg(UInt())
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when (io.mem.grant.valid && repl_way === UInt(i)) {
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val d = io.mem.grant.bits.payload.data
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data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
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}
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// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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.elsewhen (s0_valid) {
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s1_raddr := s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth)
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}
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// if s1_tag_match is critical, replace with partial tag check
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when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
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}
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val finish_q = Module(new Queue(new GrantAck, 1))
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finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload)
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finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
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// output signals
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io.resp.valid := s2_hit
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io.mem.acquire.meta.valid := (state === s_request) && finish_q.io.enq.ready
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io.mem.acquire.meta.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0))
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io.mem.acquire.data.valid := Bool(false)
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io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq)
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io.mem.grant.ready := Bool(true)
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// control state machine
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switch (state) {
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is (s_ready) {
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when (s2_miss) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request) {
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when (io.mem.acquire.meta.ready && finish_q.io.enq.ready) { state := s_refill_wait }
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}
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is (s_refill_wait) {
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when (io.mem.grant.valid) { state := s_refill }
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}
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is (s_refill) {
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when (refill_done) { state := s_ready }
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}
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}
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}
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