51 lines
1.5 KiB
Scala
51 lines
1.5 KiB
Scala
package rocket
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import Chisel._
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import Constants._
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class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
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{
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val io = new Bundle {
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val out_fast = new FIFOIO()(data).flip
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val out_slow = new FIFOIO()(data)
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val in_fast = new FIFOIO()(data)
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val in_slow = new FIFOIO()(data).flip
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val clk_slow = Bool(OUTPUT)
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}
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val hold_cycles = if (hold_cycles_in == -1) divisor/4 else hold_cycles_in
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require((divisor & (divisor-1)) == 0)
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require(hold_cycles < divisor/2 && hold_cycles >= 1)
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val cnt = Reg() { UFix(width = log2Up(divisor)) }
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cnt := cnt + UFix(1)
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val out_en = cnt === UFix(divisor/2+hold_cycles-1) // rising edge + hold time
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val in_en = cnt === UFix(divisor/2-1) // rising edge
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val in_slow_rdy = Reg(resetVal = Bool(false))
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val out_slow_val = Reg(resetVal = Bool(false))
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val out_slow_bits = Reg() { data }
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val fromhost_q = new queue(1)(data)
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fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
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fromhost_q.io.enq.bits := io.in_slow.bits
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fromhost_q.io.deq <> io.in_fast
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val tohost_q = new queue(1)(data)
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tohost_q.io.enq <> io.out_fast
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tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val
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when (out_en) {
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in_slow_rdy := fromhost_q.io.enq.ready
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out_slow_val := tohost_q.io.deq.valid
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out_slow_bits := Mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
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}
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io.in_slow.ready := in_slow_rdy
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io.out_slow.valid := out_slow_val
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io.out_slow.bits := out_slow_bits
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io.clk_slow := cnt(log2Up(divisor)-1).toBool
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}
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