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riscv
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rocket-chip
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861651587b
rocket-chip
/
src
/
main
/
scala
History
Megan Wachs
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (
#615
)
2017-03-27 03:29:07 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (
#507
)
2017-01-13 14:41:19 -08:00
coreplex
RocketTile: Create a wrapper for SyncRocketTile as well (
#616
)
2017-03-27 02:45:37 -07:00
diplomacy
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
groundtest
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
jtag
Add ucb-art/chisel-jtag (
#612
)
2017-03-26 18:03:21 -07:00
junctions
Fixed Hasti can't handle N masters to one slave
#571
(
#576
)
2017-03-13 20:36:53 -07:00
regmapper
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
rocket
RocketTile: Create a wrapper for SyncRocketTile as well (
#616
)
2017-03-27 02:45:37 -07:00
rocketchip
coreplex: move buffers inside the coreplex
2017-03-24 22:54:48 -07:00
tile
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
uncore
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
2017-03-26 20:58:14 -07:00
unittest
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
util
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (
#615
)
2017-03-27 03:29:07 -07:00