Andrew Waterman 8e63f4a1a5 Remove ClockToSignal and vice-versa ... Clock.asUInt and Bool.asClock now suffice.		2016-09-21 16:17:14 -07:00
..
.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	Use PROJECT rather than MODEL in name of binary and generated src files.	2016-09-19 13:23:17 -07:00
Makefrag	Remove ClockToSignal and vice-versa	2016-09-21 16:17:14 -07:00
Makefrag-verilog	[testharness] vsim makefrag cleanup	2016-09-19 15:14:45 -07:00
vlsi_mem_gen	fix null statement in vsli_mem_gen ala firrtl#264 (#252)	2016-09-07 11:04:36 -07:00