302 lines
12 KiB
Verilog
Executable File
302 lines
12 KiB
Verilog
Executable File
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module DebugTransportModuleJtag (
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//JTAG Interface
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jtag_TDI,
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jtag_TDO,
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jtag_TCK,
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jtag_TMS,
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jtag_TRST,
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jtag_DRV_TDO,
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dtm_req_valid,
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dtm_req_ready,
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dtm_req_bits,
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dtm_resp_valid,
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dtm_resp_ready,
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dtm_resp_bits
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);
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//--------------------------------------------------------
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// Parameter Declarations
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parameter DEBUG_DATA_BITS = 34;
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parameter DEBUG_ADDR_BITS = 5; // Spec allows values are 5-7
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parameter DEBUG_OP_BITS = 2; // OP and RESP are the same size.
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parameter JTAG_VERSION = 4'h1;
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parameter JTAG_PART_NUM = 16'h0E31; // E31
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parameter JTAG_MANUF_ID = 11'h489; // As Assigned by JEDEC
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localparam IR_BITS = 5;
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localparam DEBUG_VERSION = 0;
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// JTAG State Machine
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localparam TEST_LOGIC_RESET = 4'h0;
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localparam RUN_TEST_IDLE = 4'h1;
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localparam SELECT_DR = 4'h2;
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localparam CAPTURE_DR = 4'h3;
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localparam SHIFT_DR = 4'h4;
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localparam EXIT1_DR = 4'h5;
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localparam PAUSE_DR = 4'h6;
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localparam EXIT2_DR = 4'h7;
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localparam UPDATE_DR = 4'h8;
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localparam SELECT_IR = 4'h9;
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localparam CAPTURE_IR = 4'hA;
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localparam SHIFT_IR = 4'hB;
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localparam EXIT1_IR = 4'hC;
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localparam PAUSE_IR = 4'hD;
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localparam EXIT2_IR = 4'hE;
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localparam UPDATE_IR = 4'hF;
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//RISCV DTM Registers (see RISC-V Debug Specification)
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// All others are treated as 'BYPASS'.
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localparam REG_BYPASS = 5'b11111;
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localparam REG_IDCODE = 5'b00001;
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localparam REG_DEBUG_ACCESS = 5'b10001;
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localparam REG_DTM_INFO = 5'b10000;
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localparam DBUS_REG_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
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localparam DBUS_REQ_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
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localparam DBUS_RESP_BITS = DEBUG_OP_BITS + DEBUG_DATA_BITS;
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localparam SHIFT_REG_BITS = DBUS_REG_BITS;
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//--------------------------------------------------------
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// I/O Declarations
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//JTAG SIDE
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input jtag_TDI;
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output reg jtag_TDO;
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input jtag_TCK;
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input jtag_TMS;
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input jtag_TRST;
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// To allow tri-state outside of this block.
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output reg jtag_DRV_TDO;
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// RISC-V Core Side
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output dtm_req_valid;
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input dtm_req_ready;
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output [DBUS_REQ_BITS - 1 :0] dtm_req_bits;
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input dtm_resp_valid;
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output dtm_resp_ready;
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input [DBUS_RESP_BITS - 1 : 0] dtm_resp_bits;
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//--------------------------------------------------------
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// Reg and Wire Declarations
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reg [IR_BITS -1 : 0 ] irReg;
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wire [31:0] idcode;
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wire [31:0] dtminfo;
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reg [DBUS_REG_BITS - 1 : 0] dbusReg;
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reg dbusValidReg;
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reg [3:0] jtagStateReg;
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reg [SHIFT_REG_BITS -1 : 0] shiftReg;
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reg doDbusWriteReg;
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reg doDbusReadReg;
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reg busyReg;
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reg skipOpReg; // Skip op because we're busy.
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reg downgradeOpReg; // Downgrade op because prev. op failed.
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wire busy;
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wire nonzeroResp;
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wire [SHIFT_REG_BITS -1 : 0] busyResponse;
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wire [SHIFT_REG_BITS -1 : 0] nonbusyResponse;
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//--------------------------------------------------------
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// Combo Logic
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assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1};
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wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
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wire [3:0] debugVersion = DEBUG_VERSION[3:0];
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assign dtminfo = {24'b0, debugAddrBits, debugVersion};
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//busy, dtm_resp* is only valid during CAPTURE_DR,
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// so these signals should only be used at that time.
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// This assumes there is only one transaction in flight at a time.
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assign busy = busyReg & ~dtm_resp_valid;
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// This is needed especially for the first request.
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assign nonzeroResp = dtm_resp_valid ? |{dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0;
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// Interface to DM.
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// Note that this means dtm_resp_bits must only be used during CAPTURE_DR.
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assign dtm_resp_ready = (jtagStateReg == CAPTURE_DR) &&
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(irReg == REG_DEBUG_ACCESS) &&
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dtm_resp_valid;
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assign dtm_req_valid = dbusValidReg;
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assign dtm_req_bits = dbusReg;
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assign busyResponse = {{(DEBUG_ADDR_BITS + DEBUG_DATA_BITS){1'b0}},
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{(DEBUG_OP_BITS){1'b1}}}; // Generalizing 'busy' to 'all-1'
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assign nonbusyResponse = {dbusReg[(DEBUG_DATA_BITS + DEBUG_OP_BITS) +: DEBUG_ADDR_BITS] , // retain address bits from Req.
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dtm_resp_bits[DEBUG_OP_BITS +: DEBUG_DATA_BITS] , // data
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dtm_resp_bits[0 +: DEBUG_OP_BITS] // response
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};
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//--------------------------------------------------------
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// Sequential Logic
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// JTAG STATE MACHINE
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always @(posedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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jtagStateReg <= TEST_LOGIC_RESET;
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end else begin
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case (jtagStateReg)
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TEST_LOGIC_RESET : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
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RUN_TEST_IDLE : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
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SELECT_DR : jtagStateReg <= jtag_TMS ? SELECT_IR : CAPTURE_DR;
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CAPTURE_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
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SHIFT_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
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EXIT1_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : PAUSE_DR;
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PAUSE_DR : jtagStateReg <= jtag_TMS ? EXIT2_DR : PAUSE_DR;
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EXIT2_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : SHIFT_DR;
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UPDATE_DR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
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SELECT_IR : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : CAPTURE_IR;
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CAPTURE_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
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SHIFT_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
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EXIT1_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : PAUSE_IR;
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PAUSE_IR : jtagStateReg <= jtag_TMS ? EXIT2_IR : PAUSE_IR;
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EXIT2_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : SHIFT_IR;
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UPDATE_IR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
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endcase // case (jtagStateReg)
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end // else: !if(jtag_TRST)
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end // always @ (posedge jtag_TCK or posedge jtag_TRST)
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// SHIFT REG
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always @(posedge jtag_TCK) begin
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case (jtagStateReg)
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CAPTURE_IR : shiftReg <= {{(SHIFT_REG_BITS-1){1'b0}}, 1'b1}; //JTAG spec only says must end with 'b01.
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SHIFT_IR : shiftReg <= {{(SHIFT_REG_BITS-IR_BITS){1'b0}}, jtag_TDI, shiftReg[IR_BITS-1 : 1]};
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CAPTURE_DR : case (irReg)
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REG_BYPASS : shiftReg <= {(SHIFT_REG_BITS){1'b0}};
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REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, idcode};
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REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, dtminfo};
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REG_DEBUG_ACCESS : shiftReg <= busy ? busyResponse : nonbusyResponse;
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default : //BYPASS
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shiftReg <= {(SHIFT_REG_BITS){1'b0}};
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endcase
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SHIFT_DR : case (irReg)
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REG_BYPASS : shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}}, jtag_TDI};
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REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
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REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
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REG_DEBUG_ACCESS : shiftReg <= {jtag_TDI, shiftReg[SHIFT_REG_BITS -1 : 1 ]};
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default: // BYPASS
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shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}} , jtag_TDI};
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endcase // case (irReg)
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endcase // case (jtagStateReg)
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end
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// IR
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always @(negedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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irReg <= REG_IDCODE;
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end else if (jtagStateReg == TEST_LOGIC_RESET) begin
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irReg <= REG_IDCODE;
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end else if (jtagStateReg == UPDATE_IR) begin
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irReg <= shiftReg[IR_BITS-1:0];
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end
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end
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// Busy. We become busy when we first try to send a request.
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// We stop being busy when we accept a response.
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// This means that busyReg will still be set when we check it,
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// so the logic for checking busy looks ahead.
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always @(posedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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busyReg <= 1'b0;
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end else if (dtm_req_valid) begin //UPDATE_DR onwards
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busyReg <= 1'b1;
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end else if (dtm_resp_valid & dtm_resp_ready) begin //only in CAPTURE_DR
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busyReg <= 1'b0;
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end
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end // always @ (posedge jtag_TCK or posedge jtag_TRST)
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// Downgrade/Skip. We make the decision to downgrade or skip
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// during every CAPTURE_DR, and use the result in UPDATE_DR.
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always @(posedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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skipOpReg <= 1'b0;
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downgradeOpReg <= 1'b0;
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end else if (irReg == REG_DEBUG_ACCESS) begin
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case(jtagStateReg)
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CAPTURE_DR: begin
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skipOpReg <= busy;
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downgradeOpReg <= (~busy & nonzeroResp);
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end
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UPDATE_DR: begin
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skipOpReg <= 1'b0;
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downgradeOpReg <= 1'b0;
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end
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endcase // case (jtagStateReg)
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end
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end // always @ (posedge jtag_TCK or posedge jtag_TRST)
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//dbusReg, dbusValidReg.
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always @(posedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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dbusReg <= {(DBUS_REG_BITS) {1'b0}};
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dbusValidReg <= 1'b0;
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end else if (jtagStateReg == UPDATE_DR) begin
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if (irReg == REG_DEBUG_ACCESS) begin
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if (skipOpReg) begin
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// do nothing.
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end else if (downgradeOpReg) begin
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dbusReg <= {(DBUS_REG_BITS){1'b0}}; // NOP has encoding 2'b00.
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dbusValidReg <= 1'b1;
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end else begin
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dbusReg <= shiftReg[DBUS_REG_BITS-1:0];
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dbusValidReg <= 1'b1;
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end
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end
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end else if (dtm_req_ready) begin
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dbusValidReg <= 1'b0;
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end
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end // always @ (negedge jtag_TCK or posedge jtag_TRST)
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//TDO
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always @(negedge jtag_TCK or posedge jtag_TRST) begin
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if (jtag_TRST) begin
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jtag_TDO <= 1'b0;
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jtag_DRV_TDO <= 1'b0;
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end else if (jtagStateReg == SHIFT_IR) begin
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jtag_TDO <= shiftReg[0];
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jtag_DRV_TDO <= 1'b1;
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end else if (jtagStateReg == SHIFT_DR) begin
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jtag_TDO <= shiftReg[0];
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jtag_DRV_TDO <= 1'b1;
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end else begin
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jtag_TDO <= 1'b0;
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jtag_DRV_TDO <= 1'b0;
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end
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end // always @ (negedge jtag_TCK or posedge jtag_TRST)
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endmodule
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