c5838dd9b3
Until recently, we were assuming that the data channel in AXI was always right-justified. However, for narrow writes, the data must actually be aligned within the byte lanes. This commit changes some of the converters in order to fix this issue. There was a bug in the L2 cache in which a merged get request was causing the tracker to read the old data from the data array, overwriting the updated data acquired from outer memory. Changed it so that pending_reads is no longer set if the data in the buffer is already valid. There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and FinishToDst types used client_id for routing to managers. This caused bits to get cut off, which meant the Finish messages could not be routed correctly. Changed to use manager_id instead. |
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| .. | ||
| Configs.scala | ||
| DeviceSet.scala | ||
| Fpga.scala | ||
| RocketChip.scala | ||
| TestBench.scala | ||
| TestConfigs.scala | ||
| Testing.scala | ||
| Vlsi.scala | ||
| ZscaleChip.scala | ||