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riscv/rocket-chip
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7ae6bf761134f8b9d7a41d48dbb5006c3d36cb45
rocket-chip/src/main/scala
T
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Megan Wachs 4449dd0baa Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
..
amba
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
config
config: fix warning
2017-09-22 14:58:36 -07:00
coreplex
tile: BaseTile refactor, pt 2
2018-01-02 15:37:31 -08:00
devices
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
diplomacy
tile: BaseTile refactor, pt 1
2017-12-26 11:04:15 -08:00
groundtest
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
interrupts
diplomacy: provide a val name for all LazyModule constructions
2017-12-01 11:28:21 -08:00
jtag
JTAG: Revert to Chisel._ for Issue 1160 (#1161)
2017-12-18 21:02:31 -08:00
regmapper
regmapper: fix d_ready => d_bits loop in RegField.bytes
2017-11-30 16:38:45 -08:00
rocket
Merge pull request #1171 from freechipsproject/fix-msb-check
2018-01-03 12:06:18 -08:00
system
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
2018-01-05 16:02:52 -08:00
tile
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
tilelink
tile: BaseTile refactor, pt 1
2017-12-26 11:04:15 -08:00
unittest
unittest: add an API for describing LazyModule unit tests
2017-12-01 11:26:59 -08:00
util
Add Cross Cover Property Library (#1149)
2017-12-07 18:46:10 -08:00
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