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rocket-chip/vsrc
mwachs5 a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305)
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
..
AsyncMailbox.v This commit adds Logic & test support for JTAG implementation of Debug Transport Module. 2016-08-19 16:08:31 -07:00
AsyncResetReg.v util: Do BlackBox Async Set/Reset Registers more properly (#305) 2016-09-16 13:50:09 -07:00
AsyncSetReg.v util: Do BlackBox Async Set/Reset Registers more properly (#305) 2016-09-16 13:50:09 -07:00
ClockDivider.v tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
ClockToSignal.v Add some async/clock utilities 2016-09-14 16:30:59 -07:00
DebugTransportModuleJtag.v fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
jtag_vpi.tab Add JTAG DTM and test support in simulation 2016-08-19 16:08:17 -07:00
jtag_vpi.v fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
SignalToClock.v Add some async/clock utilities 2016-09-14 16:30:59 -07:00
SimDTM.v Write test harness in Chisel 2016-08-15 23:27:27 -07:00
TestDriver.v allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00