pbing 528deefdc7 Change SystemVerilog statement into standard Verilog (#997)

2017-09-18 10:57:07 -07:00

..

debug_rom

debug: Use flags for resume instead of program buffer. Untested.

2017-04-07 16:47:16 -07:00

.gitignore

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authors

scripts/authors: Matthew Naylor's submissions were under Berkeley terms

2016-11-27 22:15:43 -08:00

check_cache_trace.py

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check_comparator_trace.py

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copyright-file

scripts: two scripts to determine copyright holder of files

2016-11-27 22:15:38 -08:00

Makefile

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modify-copyright

scripts: two scripts to determine copyright holder of files

2016-11-27 22:15:38 -08:00

toaxe.py

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tracegen.py

[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)

2017-01-25 12:10:49 -08:00

tracegen+check.sh

get TraceGen working again

2016-09-26 17:28:21 -07:00

tracestats.py

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vlsi_mem_gen

Avoid width warning

2017-08-08 20:57:31 -07:00

vlsi_rom_gen

Change SystemVerilog statement into standard Verilog (#997)

2017-09-18 10:57:07 -07:00