31060ea8ae
Load miss writebacks happening at the same time as multiplication wasn't working. Hopefully this does it.
50 lines
1.7 KiB
Scala
50 lines
1.7 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Module
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{
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val io = new Bundle {
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val requestor = Vec.fill(n){new HellaCacheIO()(conf.dcache)}.flip
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val mem = new HellaCacheIO()(conf.dcache)
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}
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val r_valid = io.requestor.map(r => Reg(next=r.req.valid))
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io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
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io.requestor(0).req.ready := io.mem.req.ready
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for (i <- 1 until n)
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io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
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io.mem.req.bits := io.requestor(n-1).req.bits
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io.mem.req.bits.tag := Cat(io.requestor(n-1).req.bits.tag, UInt(n-1, log2Up(n)))
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for (i <- n-2 to 0 by -1) {
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val req = io.requestor(i).req
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when (req.valid) {
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io.mem.req.bits.cmd := req.bits.cmd
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io.mem.req.bits.typ := req.bits.typ
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io.mem.req.bits.addr := req.bits.addr
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io.mem.req.bits.phys := req.bits.phys
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io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n)))
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}
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when (r_valid(i)) {
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io.mem.req.bits.kill := req.bits.kill
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io.mem.req.bits.data := req.bits.data
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}
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}
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for (i <- 0 until n) {
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val resp = io.requestor(i).resp
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
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resp.valid := io.mem.resp.valid && tag_hit
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io.requestor(i).xcpt := io.mem.xcpt
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io.requestor(i).ordered := io.mem.ordered
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resp.bits := io.mem.resp.bits
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resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
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resp.bits.nack := io.mem.resp.bits.nack && tag_hit
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resp.bits.replay := io.mem.resp.bits.replay && tag_hit
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resp.bits.load_replay_next := io.mem.resp.bits.load_replay_next && tag_hit
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}
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}
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