92 lines
3.1 KiB
Scala
92 lines
3.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import rocket._
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import uncore.tilelink2._
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case object RocketConfigs extends Field[Seq[RocketConfig]]
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trait HasSynchronousRocketTiles extends CoreplexRISCVPlatform {
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val module: HasSynchronousRocketTilesModule
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val rocketTiles: Seq[RocketTile] = p(RocketConfigs).map { c =>
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LazyModule(new RocketTile(c)(p.alterPartial {
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case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
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case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
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}))}
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rocketTiles.foreach { r =>
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r.masterNodes.foreach { l1tol2.node := TLBuffer()(_) }
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r.slaveNode.foreach { _ := cbus.node }
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}
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val rocketTileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
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rocketTileIntNodes.foreach { _ := plic.intnode }
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}
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trait HasSynchronousRocketTilesBundle extends CoreplexRISCVPlatformBundle {
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val outer: HasSynchronousRocketTiles
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}
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trait HasSynchronousRocketTilesModule extends CoreplexRISCVPlatformModule {
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val outer: HasSynchronousRocketTiles
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val io: HasSynchronousRocketTilesBundle
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outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
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tile.io.hartid := UInt(i)
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tile.io.resetVector := io.resetVector
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tile.io.interrupts := outer.clint.module.io.tiles(i)
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tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.io.interrupts.meip := outer.rocketTileIntNodes(i).bundleOut(0)(0)
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tile.io.interrupts.seip.foreach(_ := outer.rocketTileIntNodes(i).bundleOut(0)(1))
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}
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}
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trait HasAsynchronousRocketTiles extends CoreplexRISCVPlatform {
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val module: HasAsynchronousRocketTilesModule
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import rocket.AsyncRocketTile
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val rocketTiles: Seq[AsyncRocketTile] = p(RocketConfigs).map { c =>
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LazyModule(new AsyncRocketTile(c)(p.alterPartial {
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case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
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case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
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}))}
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rocketTiles.foreach { r =>
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r.masterNodes.foreach { l1tol2.node := TLAsyncCrossingSink()(_) }
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r.slaveNode.foreach { _ := TLAsyncCrossingSource()(cbus.node) }
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}
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val rocketTileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
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rocketTileIntNodes.foreach { _ := plic.intnode }
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}
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trait HasAsynchronousRocketTilesBundle extends CoreplexRISCVPlatformBundle {
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val outer: HasAsynchronousRocketTiles
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait HasAsynchronousRocketTilesModule extends CoreplexRISCVPlatformModule {
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val outer: HasAsynchronousRocketTiles
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val io: HasAsynchronousRocketTilesBundle
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outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
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tile.clock := io.tcrs(i).clock
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tile.reset := io.tcrs(i).reset
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tile.io.hartid := UInt(i)
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tile.io.resetVector := io.resetVector
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tile.io.interrupts := outer.clint.module.io.tiles(i)
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tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.io.interrupts.meip := outer.rocketTileIntNodes(i).bundleOut(0)(0)
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tile.io.interrupts.seip.foreach(_ := outer.rocketTileIntNodes(i).bundleOut(0)(1))
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}
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}
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