rocket-chip/scala at 61fbe62112a5fb816df67dc77a9636f4d16c47f2 - rocket-chip - Tiband Gitea

riscv/rocket-chip

History

Wesley W. Terpstra 830d01329d RationalCrossing: add some documentation

2017-01-26 21:27:34 -08:00

..

Configs: use a uniform syntax without Match exceptions (#507 )

2017-01-13 14:41:19 -08:00

coreplex: provide coherence managers with geometry information

2017-01-23 15:50:39 -08:00

diplomacy: find names of LazyModules also in Seq() member values (#527 )

2017-01-24 18:10:37 -08:00

[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528 )

2017-01-25 12:10:49 -08:00

Refactor Tile to use cake pattern (#502 )

2017-01-16 18:24:08 -08:00

copyright: ran scripts/modify-copyright

2016-11-27 22:15:43 -08:00

rocket: L1 only needs cache-line transfer sizes

2017-01-19 19:07:14 -08:00

coreplex: support multiple memory channels via diplomatic trickery

2017-01-19 19:07:14 -08:00

RationalCrossing: add some documentation

2017-01-26 21:27:34 -08:00

tilelink2: add a rational clock crossing adapter

2017-01-26 20:07:28 -08:00

RationalCrossing: add some documentation

2017-01-26 21:27:34 -08:00