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rocket-chip/src/main/scala/tile
Andrew Waterman a3358f34a0 Fix priority inversion for two back-to-back divides (#948)
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
..
BaseTile.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Core.scala Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
FPU.scala Fix priority inversion for two back-to-back divides (#948) 2017-08-10 17:12:09 -07:00
Interrupts.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
L1Cache.scala Combine Coreplex and System Module Hierarchies (#875) 2017-07-23 08:31:04 -07:00
LazyRoCC.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
RocketTile.scala Use 1-entry queue on processor-side E-channel 2017-07-31 18:06:54 -07:00