151 lines
5.8 KiB
Scala
151 lines
5.8 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.tile
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem.SubsystemClockCrossing
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.util._
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case class RocketTileParams(
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core: RocketCoreParams = RocketCoreParams(),
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icache: Option[ICacheParams] = Some(ICacheParams()),
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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rocc: Seq[RoCCParams] = Nil,
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btb: Option[BTBParams] = Some(BTBParams()),
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dataScratchpadBytes: Int = 0,
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trace: Boolean = false,
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hcfOnUncorrectable: Boolean = false,
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name: Option[String] = Some("tile"),
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hartId: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None,
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boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
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) extends TileParams {
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require(icache.isDefined)
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require(dcache.isDefined)
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}
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class RocketTile(
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val rocketParams: RocketTileParams,
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crossing: SubsystemClockCrossing)
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(implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p)
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with HasExternalInterrupts
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with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with HasHellaCache
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with HasICacheFrontend {
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val intOutwardNode = IntIdentityNode()
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val slaveNode = TLIdentityNode()
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val masterNode = TLIdentityNode()
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val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map(s =>
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
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}
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dtim_adapter.foreach(lm => connectTLSlave(lm.node, xBytes))
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val bus_error_unit = tileParams.core.tileControlAddr map { a =>
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val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
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intOutwardNode := beu.intNode
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connectTLSlave(beu.node, xBytes)
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beu
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}
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val tile_master_blocker =
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tileParams.blockerCtrlAddr
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.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
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// TODO: this doesn't block other masters, e.g. RoCCs
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tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
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masterNode :=* tlOtherMastersNode
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DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
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def findScratchpadFromICache: Option[AddressSet] = dtim_adapter.map { s =>
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val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)
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require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
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require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
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finalNode.get.address(0)
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}
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nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt
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val dtimProperty = dtim_adapter.map(d => Map(
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"sifive,dtim" -> d.device.asProperty)).getOrElse(Nil)
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val itimProperty = tileParams.icache.flatMap(_.itimAddr.map(i => Map(
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"sifive,itim" -> frontend.icache.device.asProperty))).getOrElse(Nil)
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val cpuDevice = new Device {
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def describe(resources: ResourceBindings): Description =
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toDescription(resources)("sifive,rocket0", dtimProperty ++ itimProperty)
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}
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ResourceBinding {
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Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartId)))
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}
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override lazy val module = new RocketTileModuleImp(this)
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}
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class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
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with HasLazyRoCCModule[RocketTile]
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with HasHellaCacheModule
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with HasICacheFrontendModule {
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val core = Module(p(BuildCore)(outer.p))
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val uncorrectable = RegInit(Bool(false))
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
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outer.bus_error_unit.foreach { lm =>
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lm.module.io.errors.dcache := outer.dcache.module.io.errors
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lm.module.io.errors.icache := outer.frontend.module.io.errors
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}
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outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
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core.io.hartid := constants.hartid // Pass through the hartid
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trace.foreach { _ := core.io.trace }
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halt_and_catch_fire.foreach { _ := uncorrectable }
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.reset_vector := constants.reset_vector
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outer.frontend.module.io.hartid := constants.hartid
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outer.dcache.module.io.hartid := constants.hartid
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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core.io.ptw <> ptw.io.dpath
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roccCore.cmd <> core.io.rocc.cmd
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roccCore.exception := core.io.rocc.exception
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core.io.rocc.resp <> roccCore.resp
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.interrupt := roccCore.interrupt
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// Rocket has higher priority to DTIM than other TileLink clients
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outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem }
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when(!uncorrectable) { uncorrectable :=
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List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
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.flatMap { e => e.uncorrectable.map(_.valid) }
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.reduceOption(_||_)
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.getOrElse(false.B)
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}
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// TODO eliminate this redundancy
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val h = dcachePorts.size
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val c = core.dcacheArbPorts
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val o = outer.nDCachePorts
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require(h == c, s"port list size was $h, core expected $c")
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require(h == o, s"port list size was $h, outer counted $o")
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// TODO figure out how to move the below into their respective mix-ins
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dcacheArb.io.requestor <> dcachePorts
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ptw.io.requestor <> ptwPorts
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}
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