Andrew Waterman 51e0870e23 Separate I$ and D$ interface signals that span clock cycles ...

For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.

2016-04-01 19:30:39 -07:00

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scala

Separate I$ and D$ interface signals that span clock cycles

2016-04-01 19:30:39 -07:00