91d1880dbf
Doing this in Chisel leads to non-determinism due to shitty Verilog ordering semantis. Using an '=' ensures that all of the clock posedges fire before concurrent register updates. See "Gotcha 29: Sequential logic that requires blocking assignments" in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
22 lines
492 B
Verilog
22 lines
492 B
Verilog
// See LICENSE.SiFive for license details.
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/** This black-boxes a Clock Divider.
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*
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* Because Chisel does not support
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* blocking assignments, it is impossible
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* to create a deterministic divided clock.
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*
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* @param clk_out Divided Clock
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* @param clk_in Clock Input
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*
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*/
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module ClockDivider2 (output reg clk_out, input clk_in);
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initial clk_out = 1'b0;
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always @(posedge clk_in) begin
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clk_out = ~clk_out; // Must use =, NOT <=
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end
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endmodule // ClockDivider2
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