91d1880dbf
Doing this in Chisel leads to non-determinism due to shitty Verilog ordering semantis. Using an '=' ensures that all of the clock posedges fire before concurrent register updates. See "Gotcha 29: Sequential logic that requires blocking assignments" in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills. |
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|---|---|---|
| .. | ||
| AsyncResetReg.v | ||
| ClockDivider2.v | ||
| DebugTransportModuleJtag.v | ||
| jtag_vpi.tab | ||
| jtag_vpi.v | ||
| SimDTM.v | ||
| TestDriver.v | ||