55 lines
1.9 KiB
Scala
55 lines
1.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { cp => cp },
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managerFn = { mp =>
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mp.copy(managers = mp.managers.map { m =>
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val filtered = m.address.map(_.intersect(select)).flatten
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val alignment = select.alignment /* alignment 0 means 'select' selected everything */
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val maxTransfer = 1 << 30
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val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
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val cap = TransferSizes(1, capTransfer)
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if (filtered.isEmpty) { None } else {
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Some(m.copy(
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address = filtered,
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supportsAcquireT = m.supportsAcquireT .intersect(cap),
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supportsAcquireB = m.supportsAcquireB .intersect(cap),
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supportsArithmetic = m.supportsArithmetic.intersect(cap),
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supportsLogical = m.supportsLogical .intersect(cap),
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supportsGet = m.supportsGet .intersect(cap),
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supportsPutFull = m.supportsPutFull .intersect(cap),
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supportsPutPartial = m.supportsPutPartial.intersect(cap),
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supportsHint = m.supportsHint .intersect(cap)))
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}
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}.flatten)
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})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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io.out <> io.in
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}
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}
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object TLFilter
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{
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply(select: AddressSet)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val filter = LazyModule(new TLFilter(select))
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filter.node := x
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filter.node
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}
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}
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