28 lines
866 B
Scala
28 lines
866 B
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.chip._
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class GroundTestTop(implicit p: Parameters) extends BaseSystem
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with HasPeripheryMasterAXI4MemPort
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with HasPeripheryTestRAMSlave {
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override lazy val module = new GroundTestTopModule(this)
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val coreplex = LazyModule(new GroundTestCoreplex)
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
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}
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class GroundTestTopModule[+L <: GroundTestTop](_outer: L) extends BaseSystemModule(_outer)
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with HasPeripheryMasterAXI4MemPortModuleImp {
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val io_success = IO(Bool(OUTPUT))
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io_success := outer.coreplex.module.io.success
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}
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