47 lines
1.5 KiB
Scala
47 lines
1.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tile._
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import scala.math.max
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case object TileId extends Field[Int]
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class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
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val tileParams = p(GroundTestTilesKey)
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val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
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c.build(i, p.alterPartial {
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case TileKey => c
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case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
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})
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)}
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val fixer = LazyModule(new TLFIFOFixer)
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tile_splitter.node :=* fixer.node
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tiles.foreach { fixer.node :=* _.masterNode }
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val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBeatBytes))
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pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
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override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
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}
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class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) {
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val success = Bool(OUTPUT)
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}
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class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) {
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outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
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val status = DebugCombiner(outer.tiles.map(_.module.io.status))
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io.success := status.finished
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}
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