96 lines
2.5 KiB
Scala
96 lines
2.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.chip
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import Chisel._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.jtag.JTAGIO
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class TestHarness()(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val dut = Module(LazyModule(new ExampleRocketTop).module)
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dut.reset := reset | dut.debug.ndreset
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dut.tieOffInterrupts()
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dut.connectSimAXIMem()
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dut.connectSimAXIMMIO()
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dut.tieOffAXI4SlavePort()
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dut.connectDebug(clock, reset, io.success)
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}
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class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) extends LazyModule {
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val config = p(ExtMem)
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val totalSize = if (forceSize > 0) forceSize else BigInt(config.size)
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val size = totalSize / channels
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require(totalSize % channels == 0)
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val node = AXI4BlindInputNode(Seq.fill(channels) {
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AXI4MasterPortParameters(Seq(AXI4MasterParameters(
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name = "dut",
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id = IdRange(0, 1 << config.idBits))))})
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for (i <- 0 until channels) {
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val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
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sram.node := AXI4Buffer()(AXI4Fragmenter()(node))
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}
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val axi4 = node.bundleIn
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}
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}
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}
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class SimDTM(implicit p: Parameters) extends BlackBox {
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val io = new Bundle {
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val clk = Clock(INPUT)
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val reset = Bool(INPUT)
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val debug = new DMIIO
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val exit = UInt(OUTPUT, 32)
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}
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def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
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io.clk := tbclk
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io.reset := tbreset
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dutio.dmi <> io.debug
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dutio.dmiClock := tbclk
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dutio.dmiReset := tbreset
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tbsuccess := io.exit === UInt(1)
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when (io.exit >= UInt(2)) {
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printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
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stop(1)
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}
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}
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}
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class JTAGVPI(implicit val p: Parameters) extends BlackBox {
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val io = new Bundle {
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val jtag = new JTAGIO(hasTRSTn = false)
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val enable = Bool(INPUT)
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val init_done = Bool(INPUT)
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}
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def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = {
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dutio <> io.jtag
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dutio.TRSTn.foreach{ _:= false.B}
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jtag_reset := tbreset
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io.enable := ~tbreset
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io.init_done := ~tbreset
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// Success is determined by the gdbserver
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// which is controlling this simulation.
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tbsuccess := Bool(false)
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}
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}
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